Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
Embedded Chipathon design
| Die | 3.93 × 5.12 mm (20.1 mm²) |
|---|---|
| Core area | 12.90 mm² inside the pad ring
the project template's, 442 µm in from each edge |
| Inside the seal ring | 19.65 mm² (the die less its 26 µm seal ring) |
| Placements | 1 on the reticle, in slot F2 |
| Bond pads | 162 |
| Transistors | 80,297 |
| Logic cells | 0 + 52 filler and tap cells |
| SRAM | No SRAM |
Submission
| Licence | MIT declared
Repository: MIT in LICENSE — agrees |
|---|---|
| Template | wafer-space/gf180mcu-project-template from its README |
| How it was checked | Commit and PDK pinThe licence and template were read from the repository at commit 85e9753659e8. |
| Chip-on-board | Not selected at submission |
| Precheck | Passed
the check it was accepted on, 2026-01-03, gf180mcu-precheck 1.5.5 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3 step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 3.3 V | 3,440 custom transistors |
|---|---|
| 5 V | 1,329 custom transistors |
| Gate oxides | Thin (3.3 V) and thick (5 V/6 V) in the design itself |
| MIM capacitors | 50 (5,897 µm², between Metal4 and Metal5) |
| High-resistance poly resistors | 275 (1,810 µm²) |
| Unsalicided poly resistors | 31 (12,004 µm²) |
| Diodes | 242 (24,009 µm²) |
| Deep N-well | 13 (39,091 µm²) |
| Bipolar transistors | 32 (67 µm²) |
| I/O library | gf180mcu_fd_io (1490 cells), gf180mcu_ws_io (18 cells) |
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. MOS2 was accepted on this check, and has been checked again since with newer rules.
All 15 steps passed, with 0 KLayout DRC errors, on 2026-01-03.
Every step, and the latest re-run
| Step | Accepted on check 215, 2026-01-03, initial, gf180mcu-precheck 1.5.5 (from its image) PDK wafer-space/gf180mcu 1.6.6, LibreLane e2f0b0e | Latest re-run check 729, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1 |
|---|---|---|
| KLayout.ReadLayout | passed | passed |
| KLayout.CheckTopLevel | passed | passed |
| KLayout.CheckSize | passed | passed |
| KLayout.GenerateID | passed | passed |
| KLayout.Render | not in this flow | passed |
| KLayout.Density | passed | passed |
| Checker.KLayoutDensity | passed | passed |
| KLayout.ZeroAreaPolygons | passed | passed |
| Checker.KLayoutZeroAreaPolygons | passed | passed |
| KLayout.Antenna | passed | passed |
| Checker.KLayoutAntenna | passed | passed |
| Magic.DRC | passed | passed |
| Checker.MagicDRC | passed | passed |
| KLayout.DRC | passed | passed |
| Checker.KLayoutDRC | passed | passed |
| KLayout.WriteLayout | passed | passed |
| KLayout DRC errors | 0 | 0 |
| Magic DRC errors (advisory) | 0 | 0 |
| Files | steps · log (gzip) | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.