Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Inside the core logic cells per mm² | 14k
(18% of buffer maximum) over the 12.92 mm² core: what the design itself packed |
|---|---|
| Inside the seal ring logic cells per mm² | 9k
over all 19.65 mm² of the slot, pad ring included |
| Densest mm² logic cells per mm² | 40k (52% of buffer maximum) |
| Core covered by logic | 29% |
| Transistor density transistors per mm² | 243k average, 294k in the mm² with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
This wafer.space tapeout includes various projects from the IICQC at JKU and a TinyWhisper RISC-V from JMU.
GitHub Link: https://github.com/iic-jku/gf180mcu-jku-projects
Source repository Bonding results
| Die | 3.93 × 5.12 mm (20.1 mm²) |
|---|---|
| Core area | 12.92 mm² inside the pad ring
as set in the design's own layout settings |
| Inside the seal ring | 19.65 mm² (the die less its 26 µm seal ring) |
| Placements | 1 on the reticle, in slot F5 |
| Bond pads | 74 |
| Transistors | 3,136,970 |
| Logic cells | 174,469 + 395,678 filler and tap cells |
| Libraries | 7t-5V (174k) |
| SRAM | No SRAM |
Submission
| Licence | Apache-2.0 declared
Repository: SHL-2.1 in LICENSE, not the declared licence |
|---|---|
| Template | wafer-space/gf180mcu-project-template 1.3.5 |
| How it was checked | Commit and PDK pinThe licence and template were read from the repository at commit ebfc69daad23.The template release named above is the one whose Makefile pins the same PDK as that commit (PDK_TAG 1.6.6). |
| Chip-on-board | Not selected at submission · bonding results |
| Precheck | Passed
the check it was accepted on, 2025-12-15
Passed latest re-run, 2025-12-17, gf180mcu-precheck 1.5.5 (from its image) step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
| I/O library | gf180mcu_fd_io (1124 cells), gf180mcu_ws_io (16 cells) |
Where the area went
How this design's area splits between logic cells, filler and tap cells, other and pad ring.
- Logic cells 3.77 mm² (19%)
- Filler and tap cells 8.30 mm² (41%)
- Other 0.85 mm² (4%)
- Pad ring 7.20 mm² (36%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| nand2_1 | 7t-5V | 43,602 | 2-input NAND gate |
| clkinv_1 | 7t-5V | 13,598 | Clock inverter |
| nand3_1 | 7t-5V | 13,041 | 3-input NAND gate |
| aoi21_1 | 7t-5V | 9,308 | AND-OR-Invert compound gate |
| dffq_1 | 7t-5V | 8,884 | D flip-flop (1 bit storage) |
| dlyb_1 | 7t-5V | 8,691 | Delay buffer |
| oai21_1 | 7t-5V | 7,168 | OR-AND-Invert compound gate |
| nor2_1 | 7t-5V | 7,127 | 2-input NOR gate |
| nand2_2 | 7t-5V | 5,230 | 2-input NAND gate (2x drive) |
| dffrnq_1 | 7t-5V | 4,367 | D flip-flop with reset |
Logic density map
Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (40k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.
How this design grew
TinyWhisper has been made on 2 shuttles since Nov 2025. Every version, oldest first, with this one in bold:
- Nov 2025 · Tiny Tapeout SKY 25b Tiny Whisper — 2 × 2 tiles
- Dec 2025 · wafer.space Run 1 JKU1 gf180mcu-jku-projects — 1 × 1 slot, one of the JKU projects on this die
Tiny Tapeout tile Google shuttle wafer.space die
Parts of this design are on Tiny Tapeout chips too
Tiny Tapeout puts many small designs on one chip, so trying out a block costs a fraction of a whole die: a cheap way to test one piece of a bigger design before it goes on a die of its own.
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. JKU1 was accepted on this check, and has been checked again since with newer rules.
All 15 steps passed, with 0 KLayout DRC errors, on 2025-12-15.
Every step, and the latest re-run
| Step | Accepted on check 103, 2025-12-15, initial | Latest re-run check 141, 2025-12-17, drc_update, gf180mcu-precheck 1.5.5 (from its image) PDK wafer-space/gf180mcu 1.6.6, LibreLane e2f0b0e |
|---|---|---|
| KLayout.ReadLayout | passed | passed |
| KLayout.CheckTopLevel | passed | passed |
| KLayout.CheckSize | passed | passed |
| KLayout.GenerateID | passed | passed |
| KLayout.Density | passed | passed |
| Checker.KLayoutDensity | passed | passed |
| KLayout.ZeroAreaPolygons | passed | passed |
| Checker.KLayoutZeroAreaPolygons | passed | passed |
| KLayout.Antenna | passed | passed |
| Checker.KLayoutAntenna | passed | passed |
| Magic.DRC | passed | passed |
| Checker.MagicDRC | passed | passed |
| KLayout.DRC | passed | passed |
| Checker.KLayoutDRC | passed | passed |
| KLayout.WriteLayout | passed | passed |
| KLayout DRC errors | 0 | 0 |
| Magic DRC errors (advisory) | 0 | 0 |
| Files | steps · log (gzip) | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.