Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
We, ISHI-KAI, are a community that promotes open source PDK & EDA.
This time, we brought together 14 novice semiconductor designers (most of whom were new to semiconductor design), each of whom created an analog circuit, such as an Inverter or OPAMP, ADC, PLL, BGR, CS, made using xschem & klayout with P-Cells .
All schematics and layouts are released under an open source license.
In addition, pads for probing were added to all circuits, taking into account that only bare dies are received.
Since ISHI-KAI has university professors and semiconductor companies as collaborators, we are able to borrow probers through the generosity of professors and companies.Therefore, we plan to run analog circuits by probing.
Source repository Die photographBonding results
| Die | 3.93 × 5.12 mm (20.1 mm²) |
|---|---|
| Core area | 12.90 mm² inside the pad ring
the project template's, 442 µm in from each edge |
| Inside the seal ring | 19.65 mm² (the die less its 26 µm seal ring) |
| Placements | 1 on the reticle, in slot G3 |
| Bond pads | 74 |
| Probe pads | 109 |
| Transistors | 58,233 |
| Logic cells | 0 + 63 filler and tap cells |
| SRAM | No SRAM |
Submission
| Licence | Apache-2.0 declared
Repository: Apache-2.0 in LICENSE — agrees |
|---|---|
| How it was checked | Commit and PDK pinThe licence and template were read from the repository at commit ae2164f44677. |
| Chip-on-board | Not selected at submission · bonding results |
| Precheck | Passed
the check it was accepted on, 2026-01-04, gf180mcu-precheck 1.5.5 (from its image)
step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 3.3 V | 9,268 custom transistors |
|---|---|
| 5 V | 4,781 custom transistors |
| 6 V | 90 custom transistors |
| Gate oxides | Thin (3.3 V) and thick (5 V/6 V) in the design itself |
| MIM capacitors | 95 (13,937 µm², between Metal4 and Metal5) |
| High-resistance poly resistors | 33 (660 µm²) |
| Unsalicided poly resistors | 438 (32,465 µm²) |
| Diodes | 64 (307 µm²) |
| Deep N-well | 73 (19,484 µm²) |
| I/O library | gf180mcu_fd_io (1119 cells), gf180mcu_ws_io (21 cells) |
The fabricated die
A photograph of the finished chip, taken through a microscope after manufacture: optical micrograph © 2026 InfoSecDJ, CC BY-SA 4.0
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. ISHI was accepted on this check.
All 15 steps passed, with 0 KLayout DRC errors, on 2026-01-04.
Every step
| Step | Accepted on, and latest check 240, 2026-01-04, initial, gf180mcu-precheck 1.5.5 (from its image) PDK wafer-space/gf180mcu 1.6.6, LibreLane e2f0b0e |
|---|---|
| KLayout.ReadLayout | passed |
| KLayout.CheckTopLevel | passed |
| KLayout.CheckSize | passed |
| KLayout.GenerateID | passed |
| KLayout.Density | passed |
| Checker.KLayoutDensity | passed |
| KLayout.ZeroAreaPolygons | passed |
| Checker.KLayoutZeroAreaPolygons | passed |
| KLayout.Antenna | passed |
| Checker.KLayoutAntenna | passed |
| Magic.DRC | passed |
| Checker.MagicDRC | passed |
| KLayout.DRC | passed |
| Checker.KLayoutDRC | passed |
| KLayout.WriteLayout | passed |
| KLayout DRC errors | 0 |
| Magic DRC errors (advisory) | 0 |
| Files | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.