Tiny Tapeout GF 0.3 · Die T0P3 on wafer.space Run 2

Abad2048

258 · FPGA · 1 × 2 tiles

by Alexander Co Abad

Layout render of Abad2048

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		21k (28% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		30k (40% of buffer maximum)
Core covered by logic58%
Transistor density
transistors per mm²		279k average, 314k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Colorful 2048 game uploaded successfully to the TT FPGA with game pmod!

Source repository Its page on Tiny TapeoutBuy a chip and board

Size347 × 325 µm (0.113 mm²)
Macrott_um_AbAdA_2048
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.3
Tiles1 × 2 at column 2, row 5 of the tile grid
Mux address258
LanguageVerilog
Clock25.175 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors32,221
Logic cells2,452 + 4,224 filler and tap cells
Libraries 7t-5V (2k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

58%
36%
  • Logic cells 0.07 mm² (58%)
  • Filler and tap cells 0.04 mm² (36%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 3422-input NAND gate
dffq_17t-5V 289D flip-flop (1 bit storage)
nor2_17t-5V 1992-input NOR gate
oai21_17t-5V 154OR-AND-Invert compound gate
aoi21_17t-5V 125AND-OR-Invert compound gate
clkinv_17t-5V 115Clock inverter
dlyb_17t-5V 96Delay buffer
nand3_17t-5V 713-input NAND gate
mux2_27t-5V 662-input multiplexer (2x drive)
oai211_17t-5V 63OR-AND-Invert compound gate

Logic density map

169 logic cells, 2,604 transistors 283 logic cells, 3,056 transistors 269 logic cells, 2,959 transistors 74 logic cells, 1,118 transistors 196 logic cells, 2,825 transistors 268 logic cells, 2,996 transistors 244 logic cells, 3,345 transistors 105 logic cells, 1,342 transistors 204 logic cells, 2,798 transistors 215 logic cells, 2,887 transistors 206 logic cells, 2,892 transistors 89 logic cells, 1,266 transistors 26 logic cells, 573 transistors 35 logic cells, 628 transistors 46 logic cells, 646 transistors 23 logic cells, 286 transistors Densest SRAM-free 0.1 mm square: 303 logic cells 17k 28k 27k 20k 27k 24k 20k 21k 21k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (30k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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