Tiny Tapeout GF 0.3 · Die T0P3 on wafer.space Run 2
256x8 SRAM
256 · Other digital · 1 × 2 tiles
by Julia Desmazes · repository @Essenceia
Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
96 logic cells: too few for density figures, which are given for projects of 1,000 or more.
Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.
256x8 SRAM for testing
Source repository Its page on Tiny TapeoutBuy a chip and board
| Size | 347 × 325 µm (0.113 mm²) |
|---|---|
| Macro | tt_um_essen |
| Files | documentation · licence · layout and netlist in Tiny Tapeout GF 0.3 |
| Tiles | 1 × 2 at column 3, row 5 of the tile grid |
| Mux address | 256 |
| Language | Verilog |
| Clock | 50 MHz |
| Built with | LibreLane 3.0.3, open_pdks 54435919abff |
| Transistors | 25,949 |
| Logic cells | 96 + 1,226 filler and tap cells |
| Libraries | 7t-5V (96) |
| SRAM | 1 macro, 2,048 bits |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 3.3 V | ocd SRAM |
|---|---|
| 5 V | 7t-5V standard cells |
| Gate oxides | Thin (3.3 V) and thick (5 V/6 V) in the design itself |
Where the area went
How this project's area splits between logic cells, SRAM, filler and tap cells and other.
- Logic cells 4,511 µm² (4%)
- SRAM 0.07 mm² (59%)
- Filler and tap cells 0.03 mm² (25%)
- Other 0.01 mm² (13%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| and2_1 | 7t-5V | 23 | 2-input AND gate |
| dlyb_1 | 7t-5V | 21 | Delay buffer |
| dlyc_1 | 7t-5V | 16 | Delay buffer |
| dffq_1 | 7t-5V | 15 | D flip-flop (1 bit storage) |
| dffq_2 | 7t-5V | 9 | D flip-flop (1 bit storage, 2x drive) |
| clkbuf_16 | 7t-5V | 8 | Clock buffer (16x drive) |
| clkinv_1 | 7t-5V | 2 | Clock inverter |
| buf_2 | 7t-5V | 1 | Buffer (2x drive) |
| nand2_1 | 7t-5V | 1 | 2-input NAND gate |
SRAM macros
The ready-made memory blocks this design uses.
| Macro | Count | Bits each |
|---|---|---|
| gf180mcu_ocd_ip_sram__sram256x8m8wm1 | 1 | 2,048 |
Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.