Google GF180MCU test shuttle (MPW‑18H1) · Made on a private GlobalFoundries MPW run
Analog front-end for sensor readout (OpenFASoC)
0004 · Analog and mixed-signal · 1 × 1 slot
Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
248 logic cells: too few for density figures, which are given for designs of 1,000 or more.
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
Analog front-end for reading out flexible laser-induced graphene sensors: a 14-bit SAR ADC, folded-cascode op-amps with programmable bias and bias generation, designed with open-source tools by Brown University. Published as A. Li et al., IEEE Solid-State Circuits Magazine 16(2), 2024 (doi:10.1109/MSSC.2024.3380586).
Source repository Die photographAs shipped
| Die | 3.93 × 5.12 mm (20.1 mm²) |
|---|---|
| Core area | 9.00 mm² inside the pad ring
its user_project_wrapper cell |
| Placements | 1 on the reticle |
| Bond pads | 136 |
| Transistors | 104,169 |
| Logic cells | 248 + 1,433 filler and tap cells |
| Libraries | 7t-5V (248) |
| SRAM | No SRAM |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 3.3 V | 39,217 custom transistors |
|---|---|
| 5 V | 7t-5V standard cells, 20 custom transistors |
| 6 V | 18,462 custom transistors |
| Gate oxides | Thin (3.3 V) and thick (5 V/6 V) in the design itself |
| MIM capacitors | 123 (77,176 µm², between Metal4 and Metal5) |
| High-resistance poly resistors | 20 (200 µm²) |
| Unsalicided poly resistors | 1 (9 µm²) |
| Diodes | 32,770 (6,903 µm²) |
| Deep N-well | 34 (24,736 µm²) |
| I/O library | gf180mcu_fd_io (578 cells) |
Where the area went
How this design's area splits between filler and tap cells, other and outside the user area.
- Filler and tap cells 0.01 mm² (<1%)
- Other 8.98 mm² (45%)
- Outside the user area 11.12 mm² (55%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| clkbuf_1 | 7t-5V | 39 | Clock buffer |
| clkbuf_4 | 7t-5V | 31 | Clock buffer (4x drive) |
| clkinv_4 | 7t-5V | 28 | Clock inverter (4x drive) |
| and3_1 | 7t-5V | 16 | 3-input AND gate |
| oai21_1 | 7t-5V | 15 | OR-AND-Invert compound gate |
| aoi21_1 | 7t-5V | 13 | AND-OR-Invert compound gate |
| clkinv_1 | 7t-5V | 12 | Clock inverter |
| buf_1 | 7t-5V | 10 | Buffer |
| dffq_1 | 7t-5V | 10 | D flip-flop (1 bit storage) |
| nor3_2 | 7t-5V | 8 | 3-input NOR gate (2x drive) |
The fabricated die
A photograph of the finished chip, taken through a microscope after manufacture: optical micrograph © 2025 John McMaster, CC BY 4.0
