Google GF180MCU test shuttle (MPW‑18H1) · Made on a private GlobalFoundries MPW run
Fitbit test IC 1
0003 · Test structures · 1 × 1 slot
Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
800 logic cells: too few for density figures, which are given for designs of 1,000 or more.
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
| Die | 3.93 × 5.12 mm (20.1 mm²) |
|---|---|
| Core area | 9.00 mm² inside the pad ring
its user_project_wrapper cell |
| Placements | 1 on the reticle |
| Bond pads | 63 |
| Probe pads | 44 |
| Transistors | 113,117 |
| Logic cells | 800 + 17,709 filler and tap cells |
| Libraries | 7t-5V (800) |
| SRAM | No SRAM |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 3.3 V | 7,590 custom transistors |
|---|---|
| 5 V | 7t-5V standard cells |
| Gate oxides | Thin (3.3 V) and thick (5 V/6 V) in the design itself |
| MIM capacitors | 4 (4,800 µm², between Metal4 and Metal5) |
| Unsalicided poly resistors | 2 (18 µm²) |
Where the area went
How this design's area splits between logic cells, filler and tap cells, other and outside the user area.
- Logic cells 0.02 mm² (<1%)
- Filler and tap cells 0.47 mm² (2%)
- Other 8.51 mm² (42%)
- Outside the user area 11.12 mm² (55%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| clkbuf_1 | 7t-5V | 137 | Clock buffer |
| clkbuf_3 | 7t-5V | 136 | Clock buffer (3x drive) |
| buf_1 | 7t-5V | 67 | Buffer |
| nor2_1 | 7t-5V | 58 | 2-input NOR gate |
| dlyb_1 | 7t-5V | 49 | Delay buffer |
| dffq_1 | 7t-5V | 45 | D flip-flop (1 bit storage) |
| clkbuf_2 | 7t-5V | 30 | Clock buffer (2x drive) |
| aoi21_1 | 7t-5V | 25 | AND-OR-Invert compound gate |
| mux2_2 | 7t-5V | 21 | 2-input multiplexer (2x drive) |
| nor2_2 | 7t-5V | 21 | 2-input NOR gate (2x drive) |