Google GF180MCU test shuttle (MPW‑18H1) · Made on a private GlobalFoundries MPW run
OSU 3.3V standard cell test (vlsiffra adder)
0002 · Other digital · 1 × 1 slot
Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Core average logic cells per mm² | 1k (2% of buffer maximum) |
|---|---|
| Densest mm² logic cells per mm² | 7k (15% of buffer maximum) |
| Core covered by logic | 2% |
| Transistor density transistors per mm² | 6k average, 55k in the mm² with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
32-bit adder using Anton Blanchard's vlsiffra architecture with the OSU gf180mcuC 3.3V standard cells.
| Die | 3.93 × 5.12 mm (20.1 mm²) |
|---|---|
| Core area | 9.00 mm² inside the pad ring
its user_project_wrapper cell |
| Placements | 1 on the reticle |
| Bond pads | 63 |
| Transistors | 54,594 |
| Logic cells | 7,341 + 35,623 filler and tap cells |
| Libraries | OSU 9t-3.3V (7k) |
| SRAM | No SRAM |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 3.3 V | OSU 9t-3.3V standard cells |
|---|---|
| Gate oxides | Thin only (3.3 V) in the design itself |
Where the area went
How this design's area splits between logic cells, filler and tap cells, other and outside the user area.
- Logic cells 0.22 mm² (1%)
- Filler and tap cells 0.27 mm² (1%)
- Other 8.51 mm² (42%)
- Outside the user area 11.12 mm² (55%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| nand2_1 | OSU 9t-3.3V | 1,292 | 2-input NAND gate |
| xnor2_1 | OSU 9t-3.3V | 1,182 | 2-input XNOR gate |
| nor2_1 | OSU 9t-3.3V | 1,060 | 2-input NOR gate |
| xor2_1 | OSU 9t-3.3V | 890 | 2-input XOR gate |
| clkbuf_1 | OSU 9t-3.3V | 715 | Clock buffer |
| aoi21_1 | OSU 9t-3.3V | 445 | AND-OR-Invert compound gate |
| oai21_1 | OSU 9t-3.3V | 375 | OR-AND-Invert compound gate |
| clkinv_1 | OSU 9t-3.3V | 274 | Clock inverter |
| and2_1 | OSU 9t-3.3V | 263 | 2-input AND gate |
| dff_1 | OSU 9t-3.3V | 256 | D flip-flop (1 bit storage) |
Logic density map
Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (7k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.