Google GF180MCU test shuttle (MPW‑18H1) · Made on a private GlobalFoundries MPW run

LibreSilicon Danube River test tile

0001 · Test structures · 1 × 1 slot

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

GF180MCU test structures by Philipp Gühring of LibreSilicon; Silicon Prawn identifies the die as LibreSilicon's Danube River test tile (https://gitlab.libresilicon.com/generator-tools/danube-river).

Source repository Die photograph As shipped

Die	3.93 × 5.12 mm (20.1 mm²)
Core area	9.00 mm² inside the pad ring its user_project_wrapper cell
Placements	1 on the reticle
Bond pads	63
Probe pads	460
Pad-layer labels	1,814 letters cut through the passivation
Transistors	0
Logic cells	0
SRAM	No SRAM

Where the area went

How this design's area splits between other and outside the user area.

45%

55%

Other 9.00 mm² (45%)
Outside the user area 11.12 mm² (55%)

The fabricated die

Die photograph of LibreSilicon Danube River test tile by John McMaster

John McMaster's zoomable viewer · Larger image · full resolution (very large file) · all photographs

As shipped

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