Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Inside the core logic cells per mm² | 1k
(2% of buffer maximum) over the 12.90 mm² core: what the design itself packed |
|---|---|
| Inside the seal ring logic cells per mm² | 1k
over all 19.65 mm² of the slot, pad ring included |
| Densest mm² logic cells per mm² | 5k (8% of buffer maximum) |
| Core covered by logic | 5% |
| Transistor density transistors per mm² | 22k average, 67k in the mm² with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
MOSbiusV3
| Die | 3.93 × 5.12 mm (20.1 mm²) |
|---|---|
| Core area | 12.90 mm² inside the pad ring
the project template's, 442 µm in from each edge |
| Inside the seal ring | 19.65 mm² (the die less its 26 µm seal ring) |
| Placements | 2 on the reticle, in slots C5, C4 |
| Bond pads | 74 |
| Transistors | 287,770 |
| Logic cells | 17,889 + 8,134 filler and tap cells |
| Libraries | 9t-5V (18k) |
| SRAM | No SRAM |
Submission
| Licence | proprietary declared
No public repository |
|---|---|
| Chip-on-board | Not selected at submission · bonding results |
| Precheck | Passed
the check it was accepted on, 2025-12-17, gf180mcu-precheck 1.5.5 (from its image)
Passed latest re-run, 2026-08-03, gf180mcu-precheck 1.7.3 step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 3.3 V | 81,762 custom transistors |
|---|---|
| 5 V | 9t-5V standard cells |
| 6 V | 448 custom transistors |
| Gate oxides | Thin (3.3 V) and thick (5 V/6 V) in the design itself |
| MOS capacitors | 1,524 (138,000 µm²) |
| Unsalicided poly resistors | 6 (330 µm²) |
| Salicided poly resistors | 68 (13,600 µm²) |
| Diodes | 816 (68,727 µm²) |
| I/O library | gf180mcu_fd_io (1138 cells), gf180mcu_ws_io (2 cells) |
Where the area went
How this design's area splits between logic cells, filler and tap cells, other and pad ring.
- Logic cells 0.59 mm² (3%)
- Filler and tap cells 0.05 mm² (<1%)
- Other 12.26 mm² (61%)
- Pad ring 7.22 mm² (36%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| inv_1 | 9t-5V | 6,546 | Inverter |
| latq_1 | 9t-5V | 6,500 | Latch (level-sensitive) |
| nand2_1 | 9t-5V | 3,252 | 2-input NAND gate |
| inv_20 | 9t-5V | 400 | Inverter (20x drive) |
| inv_8 | 9t-5V | 397 | Inverter (8x drive) |
| inv_4 | 9t-5V | 396 | Inverter (4x drive) |
| inv_12 | 9t-5V | 394 | Inverter (12x drive) |
| dffrnq_4 | 9t-5V | 2 | D flip-flop with reset (4x drive) |
| nand2_4 | 9t-5V | 2 | 2-input NAND gate (4x drive) |
Logic density map
Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (5k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.
The fabricated die
A photograph of the finished chip, taken through a microscope after manufacture: optical micrograph © 2026 InfoSecDJ, CC BY-SA 4.0
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. MOSB was accepted on this check, and has been checked again since with newer rules.
All 15 steps passed, with 0 KLayout DRC errors, on 2025-12-17.
Every step, and the latest re-run
| Step | Accepted on check 142, 2025-12-17, drc_update, gf180mcu-precheck 1.5.5 (from its image) PDK wafer-space/gf180mcu 1.6.6, LibreLane e2f0b0e | Latest re-run check 772, 2026-08-03, drc_update, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1 |
|---|---|---|
| KLayout.ReadLayout | passed | passed |
| KLayout.CheckTopLevel | passed | passed |
| KLayout.CheckSize | passed | passed |
| KLayout.GenerateID | passed | passed |
| KLayout.Render | not in this flow | passed |
| KLayout.Density | passed | passed |
| Checker.KLayoutDensity | passed | passed |
| KLayout.ZeroAreaPolygons | passed | passed |
| Checker.KLayoutZeroAreaPolygons | passed | passed |
| KLayout.Antenna | passed | passed |
| Checker.KLayoutAntenna | passed | passed |
| Magic.DRC | passed | passed |
| Checker.MagicDRC | passed | passed |
| KLayout.DRC | passed | passed |
| Checker.KLayoutDRC | passed | passed |
| KLayout.WriteLayout | passed | passed |
| KLayout DRC errors | 0 | 0 |
| Magic DRC errors (advisory) | 0 | 0 |
| Files | steps · log (gzip) | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.