Tiny Tapeout GF 0.3 · Die T0P3 on wafer.space Run 2

Philippine flag waving

288 · Other digital · 1 × 2 tiles

by Alexander Co Abad

Layout render of Philippine flag waving

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		18k (23% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		31k (41% of buffer maximum)
Core covered by logic43%
Transistor density
transistors per mm²		257k average, 324k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Philippine flag waving in a DVD-like screensaver with PILIPINAS text in a 7-segment style at the bottom

Source repository Its page on Tiny TapeoutBuy a chip and board

Size347 × 325 µm (0.113 mm²)
Macrott_um_combined
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.3
Tiles1 × 2 at column 3, row 14 of the tile grid
Mux address288
LanguageVerilog
Clock25.175 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors29,712
Logic cells2,028 + 3,974 filler and tap cells
Libraries 7t-5V (2k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

43%
51%
  • Logic cells 0.05 mm² (43%)
  • Filler and tap cells 0.06 mm² (51%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 2952-input NAND gate
nor2_17t-5V 1842-input NOR gate
xor2_17t-5V 1532-input XOR gate
oai21_17t-5V 141OR-AND-Invert compound gate
aoi21_17t-5V 109AND-OR-Invert compound gate
dffq_17t-5V 81D flip-flop (1 bit storage)
clkinv_17t-5V 70Clock inverter
nand3_17t-5V 633-input NAND gate
and2_17t-5V 482-input AND gate
xor2_27t-5V 432-input XOR gate (2x drive)

Logic density map

83 logic cells, 2,291 transistors 116 logic cells, 2,500 transistors 5 logic cells, 2,122 transistors 0 logic cells, 882 transistors 228 logic cells, 2,891 transistors 279 logic cells, 3,160 transistors 199 logic cells, 2,797 transistors 22 logic cells, 980 transistors 284 logic cells, 2,833 transistors 269 logic cells, 3,114 transistors 260 logic cells, 2,957 transistors 114 logic cells, 1,156 transistors 47 logic cells, 557 transistors 43 logic cells, 640 transistors 63 logic cells, 602 transistors 16 logic cells, 230 transistors Densest SRAM-free 0.1 mm square: 314 logic cells 8k 12k <1k 23k 28k 20k 28k 27k 26k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (31k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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