Tiny Tapeout GF 0.2 · Die TTP2 on wafer.space Run 1: the standard edition

Silly-Faust

102 · Other digital · 4 × 2 tiles

by Louis Ledoux, Cochard Pierre

Layout render of Silly-Faust

Rendered from the layout at 0.90 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		21k (27% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		36k (47% of buffer maximum)
Core covered by logic56%
Transistor density
transistors per mm²		286k average, 327k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Trial to use the audio circuit compiler for open silicon

Source repository Its page on Tiny TapeoutBuy this chip

Size1440 × 325 µm (0.469 mm²)
Macrott_um_gf0p2_faust_top
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles4 × 2 at column 7, row 10 of the tile grid
Mux address102
LanguageVerilog
Clock44.1 kHz
Built withLibreLane 2.4.2, open_pdks 0fe599b2afb6
Transistors135,918
Logic cells9,814 + 13,494 filler and tap cells
Libraries 7t-5V (10k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

56%
39%
  • Logic cells 0.27 mm² (56%)
  • Filler and tap cells 0.19 mm² (39%)
  • Other 0.02 mm² (4%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 1,9872-input NAND gate
dffq_17t-5V 1,032D flip-flop (1 bit storage)
oai21_17t-5V 717OR-AND-Invert compound gate
nor2_17t-5V 4902-input NOR gate
xor2_17t-5V 4552-input XOR gate
aoi21_17t-5V 386AND-OR-Invert compound gate
dlya_27t-5V 340Delay buffer (2x drive)
mux2_27t-5V 3162-input multiplexer (2x drive)
clkinv_17t-5V 310Clock inverter
xnor2_17t-5V 2762-input XNOR gate

Logic density map

99 logic cells, 2,295 transistors 246 logic cells, 2,827 transistors 217 logic cells, 2,747 transistors 310 logic cells, 3,155 transistors 243 logic cells, 3,308 transistors 278 logic cells, 3,209 transistors 308 logic cells, 2,960 transistors 183 logic cells, 3,053 transistors 353 logic cells, 3,100 transistors 227 logic cells, 2,927 transistors 260 logic cells, 2,826 transistors 239 logic cells, 2,869 transistors 79 logic cells, 2,368 transistors 0 logic cells, 2,105 transistors 0 logic cells, 759 transistors 82 logic cells, 2,481 transistors 221 logic cells, 3,078 transistors 249 logic cells, 3,047 transistors 316 logic cells, 3,346 transistors 254 logic cells, 3,809 transistors 307 logic cells, 3,543 transistors 303 logic cells, 3,304 transistors 277 logic cells, 3,178 transistors 238 logic cells, 3,118 transistors 198 logic cells, 3,065 transistors 301 logic cells, 3,126 transistors 246 logic cells, 3,020 transistors 104 logic cells, 2,657 transistors 0 logic cells, 2,193 transistors 0 logic cells, 791 transistors 4 logic cells, 2,121 transistors 285 logic cells, 3,167 transistors 293 logic cells, 3,327 transistors 208 logic cells, 3,114 transistors 302 logic cells, 3,234 transistors 301 logic cells, 3,314 transistors 242 logic cells, 3,177 transistors 253 logic cells, 3,297 transistors 306 logic cells, 3,174 transistors 302 logic cells, 3,348 transistors 222 logic cells, 3,100 transistors 303 logic cells, 3,224 transistors 133 logic cells, 2,611 transistors 0 logic cells, 2,193 transistors 0 logic cells, 790 transistors 0 logic cells, 446 transistors 34 logic cells, 598 transistors 58 logic cells, 641 transistors 44 logic cells, 667 transistors 59 logic cells, 646 transistors 80 logic cells, 678 transistors 34 logic cells, 586 transistors 29 logic cells, 628 transistors 56 logic cells, 661 transistors 75 logic cells, 658 transistors 31 logic cells, 628 transistors 20 logic cells, 511 transistors 2 logic cells, 474 transistors 0 logic cells, 471 transistors 0 logic cells, 170 transistors Densest SRAM-free 0.1 mm square: 358 logic cells 10k 25k 22k 31k 24k 28k 31k 18k 35k 23k 26k 24k 8k 0 8k 22k 25k 32k 25k 31k 30k 28k 24k 20k 30k 25k 10k 0 <1k 28k 29k 21k 30k 30k 24k 25k 31k 30k 22k 30k 13k 0

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (36k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

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Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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