Tiny Tapeout GF 0.2 · Die TTP2 on wafer.space Run 1: the standard edition

Simon's Caterpillar

103 · Other digital · 1 × 2 tiles

by htfab

Layout render of Simon's Caterpillar

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		22k (28% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		32k (42% of buffer maximum)
Core covered by logic62%
Transistor density
transistors per mm²		288k average, 354k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Port of Caterpillar Logic to Simon Says PMOD

Source repository Its page on Tiny TapeoutBuy this chip

Size347 × 325 µm (0.113 mm²)
Macrott_um_htfab_caterpillar
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles1 × 2 at column 7, row 11 of the tile grid
Mux address103
LanguageVerilog
Clock50 kHz
Built withLibreLane 2.4.2, open_pdks 0fe599b2afb6
Transistors33,261
Logic cells2,486 + 3,418 filler and tap cells
Libraries 7t-5V (2k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

62%
32%
  • Logic cells 0.07 mm² (62%)
  • Filler and tap cells 0.04 mm² (32%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 2562-input NAND gate
dffq_17t-5V 240D flip-flop (1 bit storage)
oai21_17t-5V 189OR-AND-Invert compound gate
nor2_17t-5V 1852-input NOR gate
clkinv_17t-5V 146Clock inverter
aoi21_17t-5V 145AND-OR-Invert compound gate
clkbuf_87t-5V 67Clock buffer (8x drive)
nand3_17t-5V 663-input NAND gate
dffq_27t-5V 56D flip-flop (1 bit storage, 2x drive)
xor2_17t-5V 562-input XOR gate

Logic density map

240 logic cells, 3,164 transistors 261 logic cells, 3,203 transistors 76 logic cells, 2,533 transistors 0 logic cells, 882 transistors 246 logic cells, 3,026 transistors 278 logic cells, 3,302 transistors 252 logic cells, 3,093 transistors 60 logic cells, 1,165 transistors 233 logic cells, 2,867 transistors 272 logic cells, 3,312 transistors 270 logic cells, 3,143 transistors 110 logic cells, 1,351 transistors 47 logic cells, 599 transistors 51 logic cells, 673 transistors 58 logic cells, 656 transistors 32 logic cells, 292 transistors Densest SRAM-free 0.1 mm square: 316 logic cells 24k 26k 8k 25k 28k 25k 23k 27k 27k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (32k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

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Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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