Tiny Tapeout GF 0.2 · Die TTP2 on wafer.space Run 1: the standard edition

SCµM-BLE-RX

101 · Communications · 3 × 4 tiles

by Dingyu Zhou

Layout render of SCµM-BLE-RX

Rendered from the layout at 0.67 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		28k (37% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		39k (52% of buffer maximum)
Core covered by logic74%
Transistor density
transistors per mm²		307k average, 322k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Digital Baseband for SCµM3 BLE

Source repository Its page on Tiny TapeoutBuy this chip

Size1076 × 737 µm (0.793 mm²)
Macrott_um_BLE_RX
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles3 × 4 at column 6, row 11 of the tile grid
Mux address101
LanguageSystemVerilog
Clock16 MHz
Built withLibreLane 3.0.0.dev45, open_pdks 8afc8346a57f
Transistors245,576
Logic cells22,709 + 26,034 filler and tap cells
Libraries 7t-5V (23k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

74%
24%
  • Logic cells 0.59 mm² (74%)
  • Filler and tap cells 0.19 mm² (24%)
  • Other 0.02 mm² (2%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 3,8372-input NAND gate
xor2_17t-5V 2,3892-input XOR gate
buf_27t-5V 1,946Buffer (2x drive)
oai21_17t-5V 1,813OR-AND-Invert compound gate
nor2_17t-5V 1,5112-input NOR gate
aoi21_17t-5V 1,237AND-OR-Invert compound gate
dffrnq_17t-5V 1,188D flip-flop with reset
xnor2_17t-5V 8892-input XNOR gate
dffrnq_27t-5V 866D flip-flop with reset (2x drive)
inv_17t-5V 852Inverter

Logic density map

94 logic cells, 2,354 transistors 187 logic cells, 2,686 transistors 250 logic cells, 2,831 transistors 312 logic cells, 3,031 transistors 303 logic cells, 3,043 transistors 352 logic cells, 3,095 transistors 342 logic cells, 3,063 transistors 342 logic cells, 3,280 transistors 343 logic cells, 3,071 transistors 289 logic cells, 2,820 transistors 160 logic cells, 1,881 transistors 258 logic cells, 2,898 transistors 297 logic cells, 3,138 transistors 305 logic cells, 3,180 transistors 319 logic cells, 3,189 transistors 326 logic cells, 3,204 transistors 333 logic cells, 3,280 transistors 331 logic cells, 3,238 transistors 310 logic cells, 3,186 transistors 316 logic cells, 3,236 transistors 339 logic cells, 3,255 transistors 217 logic cells, 2,245 transistors 232 logic cells, 2,924 transistors 292 logic cells, 3,176 transistors 296 logic cells, 3,197 transistors 303 logic cells, 3,204 transistors 299 logic cells, 3,251 transistors 338 logic cells, 3,358 transistors 315 logic cells, 3,294 transistors 244 logic cells, 3,204 transistors 322 logic cells, 3,308 transistors 288 logic cells, 3,212 transistors 227 logic cells, 2,251 transistors 108 logic cells, 2,850 transistors 218 logic cells, 3,292 transistors 303 logic cells, 3,186 transistors 302 logic cells, 3,166 transistors 383 logic cells, 3,296 transistors 358 logic cells, 3,205 transistors 364 logic cells, 3,319 transistors 344 logic cells, 3,184 transistors 374 logic cells, 3,321 transistors 354 logic cells, 3,281 transistors 220 logic cells, 2,237 transistors 148 logic cells, 2,843 transistors 282 logic cells, 3,212 transistors 336 logic cells, 3,170 transistors 254 logic cells, 3,241 transistors 330 logic cells, 3,211 transistors 302 logic cells, 3,191 transistors 312 logic cells, 3,167 transistors 330 logic cells, 3,222 transistors 349 logic cells, 3,203 transistors 353 logic cells, 3,167 transistors 246 logic cells, 2,278 transistors 203 logic cells, 2,840 transistors 329 logic cells, 3,208 transistors 309 logic cells, 3,200 transistors 292 logic cells, 3,235 transistors 242 logic cells, 3,316 transistors 328 logic cells, 3,150 transistors 311 logic cells, 3,177 transistors 317 logic cells, 3,185 transistors 303 logic cells, 3,242 transistors 329 logic cells, 3,209 transistors 190 logic cells, 2,184 transistors 197 logic cells, 2,965 transistors 202 logic cells, 3,216 transistors 231 logic cells, 3,242 transistors 284 logic cells, 3,214 transistors 261 logic cells, 3,232 transistors 297 logic cells, 3,146 transistors 290 logic cells, 3,158 transistors 303 logic cells, 3,165 transistors 283 logic cells, 3,194 transistors 273 logic cells, 3,151 transistors 139 logic cells, 2,027 transistors 7 logic cells, 734 transistors 37 logic cells, 923 transistors 69 logic cells, 967 transistors 91 logic cells, 1,077 transistors 103 logic cells, 1,012 transistors 112 logic cells, 980 transistors 92 logic cells, 967 transistors 94 logic cells, 1,051 transistors 94 logic cells, 1,011 transistors 46 logic cells, 863 transistors 0 logic cells, 510 transistors Densest SRAM-free 0.1 mm square: 393 logic cells 9k 19k 25k 31k 30k 35k 34k 34k 34k 29k 16k 26k 30k 30k 32k 33k 33k 33k 31k 32k 34k 22k 23k 29k 30k 30k 30k 34k 31k 24k 32k 29k 23k 11k 22k 30k 30k 38k 36k 36k 34k 37k 35k 22k 15k 28k 34k 25k 33k 30k 31k 33k 35k 35k 25k 20k 33k 31k 29k 24k 33k 31k 32k 30k 33k 19k 20k 20k 23k 28k 26k 30k 29k 30k 28k 27k 14k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (39k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

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Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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