Tiny Tapeout GF 0.1 · Made on a GlobalFoundries private MPW run
MAIN · Shared project block · 1.6 × 1.6 mm
Rendered from the layout at 1.0 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
| Core average logic cells per mm² | 25k (32% of buffer maximum) |
|---|---|
| Densest 0.1 mm square logic cells per mm² | 43k (57% of buffer maximum) |
| Core covered by logic | 72% |
| Transistor density transistors per mm² | 292k average, 292k in the 0.1 mm square with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.
Every project, synthesised and placed together as one block behind the multiplexer that selects one project at a time
| Size | 1600 × 1600 µm (2.560 mm²) |
|---|---|
| Cell | tt_main_macro |
| Transistors | 747,240 |
| Logic cells | 63,000 + 103,553 filler and tap cells |
| Libraries | 7t-5V (63k) |
| SRAM | No SRAM |
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
How this project's area splits between logic cells, filler and tap cells and other.
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| nand2_1 | 7t-5V | 9,119 | 2-input NAND gate |
| oai21_1 | 7t-5V | 4,989 | OR-AND-Invert compound gate |
| dffq_4 | 7t-5V | 4,982 | D flip-flop (1 bit storage, 4x drive) |
| nor2_1 | 7t-5V | 4,323 | 2-input NOR gate |
| aoi21_1 | 7t-5V | 3,457 | AND-OR-Invert compound gate |
| buf_4 | 7t-5V | 2,870 | Buffer (4x drive) |
| inv_1 | 7t-5V | 2,511 | Inverter |
| xor2_1 | 7t-5V | 2,224 | 2-input XOR gate |
| dffq_1 | 7t-5V | 1,778 | D flip-flop (1 bit storage) |
| mux2_2 | 7t-5V | 1,604 | 2-input multiplexer (2x drive) |
Logic cells per mm² in each 0.1 mm square of the block (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (43k logic cells per mm²), found by sliding a 0.1 mm square over the block in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.
Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.