Tiny Tapeout GF 0.1 · Made on a GlobalFoundries private MPW run
Pad test buffer
BUFR · Test structures · 0.225 × 0.075 mm
Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
4 logic cells: too few for density figures, which are given for projects of 1,000 or more.
Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.
Connects four of the chip's pins straight to the controls of a test input/output pad, so the pad cell can be driven directly, and ties off the loopback pads
| Size | 225 × 75 µm (0.017 mm²) |
|---|---|
| Cell | tt_buffer_macro |
| Transistors | 1,836 |
| Logic cells | 4 + 248 filler and tap cells |
| Libraries | 7t-5V (4) |
| SRAM | No SRAM |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.