wafer.space Run 1

LGN FashionMNIST - Logic Gate Network trained on FashionMNIST

RZML · Accelerators · 1 × 1 slot

Layout render of LGN FashionMNIST - Logic Gate Network trained on FashionMNIST

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		7k (9% of buffer maximum)
over the 12.90 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		4k
over all 19.65 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²		8k (11% of buffer maximum)
Core covered by logic23%
Transistor density
transistors per mm²		255k average, 260k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

EXPERIMENTAL!!! The world smallest image classifier. Differential Logic / Logic Gate Network trained to classify tiny 28x28 images based on FashionMNIST dataset.

Source repository

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.90 mm² inside the pad ring
the project template's, 442 µm in from each edge
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot G4 RZML on the reticle
Bond pads74
Transistors3,284,303
Logic cells88,407 + 434,355 filler and tap cells
Libraries 7t-5V (88k)
SRAMNo SRAM

Submission

Licenceproprietary declared
The repository has no licence file
Templateegorxe/gf180mcu-caravel-template
from its README
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit ddbd922a1e9d.
Chip-on-boardNot selected at submission
PrecheckPassed the check it was accepted on, 2025-12-20, gf180mcu-precheck 1.5.5 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself
I/O librarygf180mcu_fd_io (1122 cells), gf180mcu_ws_io (18 cells)

Where the area went

How this design's area splits between logic cells, filler and tap cells and pad ring.

14%
50%
36%
  • Logic cells 2.91 mm² (14%)
  • Filler and tap cells 9.99 mm² (50%)
  • Pad ring 7.22 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
buf_87t-5V 10,534Buffer (8x drive)
nand2_17t-5V 7,5982-input NAND gate
nor2_17t-5V 7,2602-input NOR gate
xor2_17t-5V 7,0892-input XOR gate
buf_27t-5V 5,805Buffer (2x drive)
xor3_17t-5V 5,1283-input XOR gate
clkbuf_87t-5V 4,496Clock buffer (8x drive)
oai21_17t-5V 4,368OR-AND-Invert compound gate
aoi21_17t-5V 4,142AND-OR-Invert compound gate
buf_127t-5V 4,037Buffer (12x drive)

Logic density map

1,946 logic cells, 78,026 transistors 3,418 logic cells, 136,584 transistors 3,669 logic cells, 137,176 transistors 1,428 logic cells, 67,737 transistors 3,597 logic cells, 138,845 transistors 7,305 logic cells, 259,596 transistors 7,670 logic cells, 258,955 transistors 3,185 logic cells, 121,475 transistors 3,584 logic cells, 138,547 transistors 7,196 logic cells, 267,633 transistors 6,811 logic cells, 261,305 transistors 3,101 logic cells, 120,903 transistors 3,621 logic cells, 138,925 transistors 8,041 logic cells, 265,364 transistors 7,697 logic cells, 261,773 transistors 3,312 logic cells, 121,639 transistors 2,012 logic cells, 93,452 transistors 4,491 logic cells, 167,206 transistors 4,318 logic cells, 165,806 transistors 2,005 logic cells, 82,510 transistors 0 logic cells, 176 transistors 0 logic cells, 256 transistors 0 logic cells, 255 transistors 0 logic cells, 159 transistors Densest SRAM-free mm²: 8,379 logic cells 2k 3k 4k 1k 4k 7k 8k 3k 4k 7k 7k 3k 4k 8k 8k 3k 2k 4k 4k 2k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (8k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. RZML was accepted on this check, and has been checked again since with newer rules.

All 15 steps passed, with 0 KLayout DRC errors, on 2025-12-20.

Every step, and the latest re-run
StepAccepted on
check 205, 2025-12-20, initial, gf180mcu-precheck 1.5.5 (from its image)
PDK wafer-space/gf180mcu 1.6.6, LibreLane e2f0b0e		Latest re-run
check 716, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Rendernot in this flowpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCpassedpassed
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)00
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

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