Tiny Tapeout GF 0.3 · Die T0P3 on wafer.space Run 2

USB CDC (Serial) Device

450 · Communications · 1 × 2 tiles

by Uri Shaked

Layout render of USB CDC (Serial) Device

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		27k (36% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		34k (44% of buffer maximum)
Core covered by logic79%
Transistor density
transistors per mm²		308k average, 326k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

USB to UART bridge, 115200 baud rate

Source repository Its page on Tiny TapeoutBuy a chip and board

Size347 × 325 µm (0.113 mm²)
Macrott_um_urish_usb_cdc
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.3
Tiles1 × 2 at column 5, row 3 of the tile grid
Mux address450
LanguageVerilog
Clock48 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors35,599
Logic cells3,155 + 2,986 filler and tap cells
Libraries 7t-5V (3k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

79%
14%
  • Logic cells 0.09 mm² (79%)
  • Filler and tap cells 0.02 mm² (14%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 3382-input NAND gate
dffrnq_17t-5V 332D flip-flop with reset
nor2_17t-5V 2472-input NOR gate
clkinv_17t-5V 217Clock inverter
oai21_17t-5V 169OR-AND-Invert compound gate
aoi21_17t-5V 160AND-OR-Invert compound gate
dlyb_17t-5V 114Delay buffer
mux2_27t-5V 1132-input multiplexer (2x drive)
nand3_17t-5V 893-input NAND gate
aoi22_17t-5V 88AND-OR-Invert (2x2 inputs)

Logic density map

282 logic cells, 3,044 transistors 296 logic cells, 3,228 transistors 269 logic cells, 3,085 transistors 130 logic cells, 1,314 transistors 268 logic cells, 3,271 transistors 318 logic cells, 3,372 transistors 299 logic cells, 3,358 transistors 98 logic cells, 1,456 transistors 293 logic cells, 3,115 transistors 295 logic cells, 3,286 transistors 281 logic cells, 3,338 transistors 123 logic cells, 1,445 transistors 59 logic cells, 656 transistors 62 logic cells, 622 transistors 50 logic cells, 705 transistors 32 logic cells, 304 transistors Densest SRAM-free 0.1 mm square: 335 logic cells 28k 30k 27k 27k 32k 30k 29k 29k 28k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (34k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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