Tiny Tapeout GF 0.2 · Die TTP2 on wafer.space Run 1: the standard edition

LISA 8-Bit Microcontroller

197 · RISC-V and CPUs · 3 × 4 tiles

by Ken Pettit

Layout render of LISA 8-Bit Microcontroller

Rendered from the layout at 0.67 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		22k (28% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		32k (43% of buffer maximum)
Core covered by logic62%
Transistor density
transistors per mm²		299k average, 308k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

8-Bit Microcontroller SOC with 128 bytes DFFRAM module

Source repository Its page on Tiny TapeoutBuy this chip

Size1076 × 737 µm (0.793 mm²)
Macrott_um_lisa
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles3 × 4 at column 6, row 6 of the tile grid
Mux address197
LanguageVerilog
Clock18 MHz
Built withLibreLane 3.0.0.dev45, open_pdks 8afc8346a57f
Transistors238,706
Logic cells17,231 + 30,872 filler and tap cells
Libraries 7t-5V (17k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

62%
35%
  • Logic cells 0.50 mm² (62%)
  • Filler and tap cells 0.28 mm² (35%)
  • Other 0.02 mm² (2%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 2,5242-input NAND gate
oai21_17t-5V 2,140OR-AND-Invert compound gate
aoi21_17t-5V 1,213AND-OR-Invert compound gate
dffq_17t-5V 1,144D flip-flop (1 bit storage)
dffq_47t-5V 1,075D flip-flop (1 bit storage, 4x drive)
aoi22_17t-5V 969AND-OR-Invert (2x2 inputs)
buf_47t-5V 962Buffer (4x drive)
inv_17t-5V 664Inverter
nor2_17t-5V 6132-input NOR gate
xor2_17t-5V 5032-input XOR gate

Logic density map

122 logic cells, 2,447 transistors 196 logic cells, 2,767 transistors 216 logic cells, 2,870 transistors 241 logic cells, 2,910 transistors 226 logic cells, 2,882 transistors 219 logic cells, 2,910 transistors 234 logic cells, 2,912 transistors 231 logic cells, 2,936 transistors 224 logic cells, 2,906 transistors 166 logic cells, 2,748 transistors 92 logic cells, 1,828 transistors 197 logic cells, 2,838 transistors 238 logic cells, 3,021 transistors 241 logic cells, 3,052 transistors 242 logic cells, 3,065 transistors 225 logic cells, 3,049 transistors 213 logic cells, 3,116 transistors 238 logic cells, 3,056 transistors 238 logic cells, 3,023 transistors 242 logic cells, 3,089 transistors 242 logic cells, 3,047 transistors 132 logic cells, 2,110 transistors 200 logic cells, 2,915 transistors 225 logic cells, 3,060 transistors 176 logic cells, 3,066 transistors 202 logic cells, 3,110 transistors 216 logic cells, 3,040 transistors 219 logic cells, 3,091 transistors 238 logic cells, 3,063 transistors 223 logic cells, 3,133 transistors 267 logic cells, 3,056 transistors 237 logic cells, 3,185 transistors 160 logic cells, 2,058 transistors 212 logic cells, 2,936 transistors 217 logic cells, 3,112 transistors 206 logic cells, 3,195 transistors 216 logic cells, 3,191 transistors 234 logic cells, 3,253 transistors 253 logic cells, 3,163 transistors 267 logic cells, 2,996 transistors 197 logic cells, 3,009 transistors 269 logic cells, 3,119 transistors 272 logic cells, 3,168 transistors 220 logic cells, 2,124 transistors 209 logic cells, 3,034 transistors 244 logic cells, 3,196 transistors 220 logic cells, 3,216 transistors 225 logic cells, 3,335 transistors 223 logic cells, 3,281 transistors 240 logic cells, 3,162 transistors 262 logic cells, 3,136 transistors 228 logic cells, 3,154 transistors 255 logic cells, 3,111 transistors 310 logic cells, 3,089 transistors 192 logic cells, 2,102 transistors 179 logic cells, 2,969 transistors 212 logic cells, 3,190 transistors 232 logic cells, 3,213 transistors 207 logic cells, 3,201 transistors 252 logic cells, 3,127 transistors 201 logic cells, 3,297 transistors 196 logic cells, 3,179 transistors 203 logic cells, 3,194 transistors 295 logic cells, 3,060 transistors 274 logic cells, 3,028 transistors 155 logic cells, 1,928 transistors 167 logic cells, 2,874 transistors 195 logic cells, 3,064 transistors 185 logic cells, 3,147 transistors 202 logic cells, 3,019 transistors 228 logic cells, 3,005 transistors 192 logic cells, 3,156 transistors 218 logic cells, 3,170 transistors 207 logic cells, 3,177 transistors 209 logic cells, 3,075 transistors 181 logic cells, 3,041 transistors 64 logic cells, 1,850 transistors 28 logic cells, 806 transistors 52 logic cells, 953 transistors 80 logic cells, 1,031 transistors 58 logic cells, 1,044 transistors 62 logic cells, 1,011 transistors 79 logic cells, 1,018 transistors 82 logic cells, 1,021 transistors 62 logic cells, 987 transistors 51 logic cells, 960 transistors 74 logic cells, 960 transistors 0 logic cells, 510 transistors Densest SRAM-free 0.1 mm square: 323 logic cells 12k 20k 22k 24k 23k 22k 23k 23k 22k 17k 9k 20k 24k 24k 24k 22k 21k 24k 24k 24k 24k 13k 20k 22k 18k 20k 22k 22k 24k 22k 27k 24k 16k 21k 22k 21k 22k 23k 25k 27k 20k 27k 27k 22k 21k 24k 22k 22k 22k 24k 26k 23k 25k 31k 19k 18k 21k 23k 21k 25k 20k 20k 20k 29k 27k 15k 17k 19k 18k 20k 23k 19k 22k 21k 21k 18k 6k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (32k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project
Buy this chip

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

← 196 Quickscope All projects easy PAL 198 →