Tiny Tapeout GF 0.2 · Die TTP2 on wafer.space Run 1: the standard edition
Zedulo TestChip1
032 · Other digital · 1 × 1 tile
by Zedulo
Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Core average logic cells per mm² | 22k (29% of buffer maximum) |
|---|---|
| Densest 0.1 mm square logic cells per mm² | 31k (41% of buffer maximum) |
| Core covered by logic | 69% |
| Transistor density transistors per mm² | 300k average, 352k in the 0.1 mm square with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.
Integration of UART and SPI IP's
Source repository Its page on Tiny TapeoutBuy this chip
| Size | 347 × 161 µm (0.056 mm²) |
|---|---|
| Macro | tt_um_zedtc1_top |
| Files | documentation · licence · layout and netlist in Tiny Tapeout GF 0.2 |
| Tiles | 1 × 1 at column 3, row 10 of the tile grid |
| Mux address | 32 |
| Language | SystemVerilog |
| Built with | LibreLane 2.4.2, open_pdks 0fe599b2afb6 |
| Transistors | 16,817 |
| Logic cells | 1,242 + 1,219 filler and tap cells |
| Libraries | 7t-5V (1k) |
| SRAM | No SRAM |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
Where the area went
How this project's area splits between logic cells, filler and tap cells and other.
- Logic cells 0.04 mm² (69%)
- Filler and tap cells 0.01 mm² (24%)
- Other 4,033 µm² (7%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| dffrnq_1 | 7t-5V | 151 | D flip-flop with reset |
| nand2_1 | 7t-5V | 146 | 2-input NAND gate |
| nor2_1 | 7t-5V | 63 | 2-input NOR gate |
| oai21_1 | 7t-5V | 59 | OR-AND-Invert compound gate |
| clkinv_1 | 7t-5V | 58 | Clock inverter |
| aoi21_1 | 7t-5V | 49 | AND-OR-Invert compound gate |
| xor2_1 | 7t-5V | 34 | 2-input XOR gate |
| buf_2 | 7t-5V | 32 | Buffer (2x drive) |
| dlya_2 | 7t-5V | 32 | Delay buffer (2x drive) |
| buf_4 | 7t-5V | 27 | Buffer (4x drive) |
Logic density map
Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (31k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.
Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.