Tiny Tapeout GF 0.2 · Die TTP2 on wafer.space Run 1: the standard edition

Tiny Tapeout Factory Test

001 · Test structures · 1 × 1 tile

by Tiny Tapeout

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

90 logic cells: too few for density figures, which are given for projects of 1,000 or more.

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Factory test module

Size347 × 161 µm (0.056 mm²)
Macrott_um_factory_test
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles1 × 1 at column 3, row 8 of the tile grid
Mux address1
LanguageVerilog
Built withLibreLane 2.4.2, open_pdks 0fe599b2afb6
Transistors11,851
Logic cells90 + 1,244 filler and tap cells
Libraries 7t-5V (90)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

87%
  • Logic cells 3,337 µm² (6%)
  • Filler and tap cells 0.05 mm² (87%)
  • Other 4,033 µm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dlyb_17t-5V 16Delay buffer
dffrnq_17t-5V 8D flip-flop with reset
nor2_17t-5V 82-input NOR gate
and2_47t-5V 72-input AND gate (4x drive)
clkbuf_37t-5V 7Clock buffer (3x drive)
aoi21_27t-5V 6AND-OR-Invert compound gate (2x drive)
aoi21_47t-5V 6AND-OR-Invert compound gate (4x drive)
clkbuf_167t-5V 3Clock buffer (16x drive)
nand2_17t-5V 32-input NAND gate
xor2_17t-5V 32-input XOR gate

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.