Tiny Tapeout GF 0.1 · Made on a GlobalFoundries private MPW run
Cell test: OSU 9-track 3.3 V cells
CEL4 · Test structures · 0.225 × 0.225 mm
Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Core average logic cells per mm² | 20k |
|---|---|
| Densest 0.1 mm square logic cells per mm² | 32k |
| Core covered by logic | 32% |
| Transistor density transistors per mm² | 52k average, 77k in the 0.1 mm square with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.
Standard cell test in Oklahoma State University's 9-track 3.3 V library (gf180mcu_osu_sc_gp9t3v3), with its wells and implants redrawn. A chain of 1,024 inverters delays a Manchester-coded counter, so the speed of the cells can be measured on the chip from its output pin; each pair of cell tests has a core supply of its own.
| Size | 225 × 225 µm (0.051 mm²) |
|---|---|
| Cell | tt_cell_macro_4 |
| Transistors | 2,742 |
| Logic cells | 1,081 + 2,531 filler and tap cells |
| Libraries | OSU 9t-3.3V (1k) |
| SRAM | No SRAM |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 3.3 V | OSU 9t-3.3V standard cells |
|---|---|
| Gate oxides | Thin only (3.3 V) in the design itself |
Where the area went
How this project's area splits between logic cells, filler and tap cells and other.
- Logic cells 0.02 mm² (32%)
- Filler and tap cells 0.02 mm² (38%)
- Other 0.02 mm² (30%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| clkinv_1 | OSU 9t-3.3V | 1,028 | Clock inverter |
| dff_1 | OSU 9t-3.3V | 12 | D flip-flop (1 bit storage) |
| nand2_1 | OSU 9t-3.3V | 9 | 2-input NAND gate |
| and2_1 | OSU 9t-3.3V | 6 | 2-input AND gate |
| oai21_1 | OSU 9t-3.3V | 5 | OR-AND-Invert compound gate |
| xnor2_1 | OSU 9t-3.3V | 5 | 2-input XNOR gate |
| aoi21_1 | OSU 9t-3.3V | 4 | AND-OR-Invert compound gate |
| clkbuf_16 | OSU 9t-3.3V | 3 | Clock buffer (16x drive) |
| xor2_1 | OSU 9t-3.3V | 3 | 2-input XOR gate |
| mux2_1 | OSU 9t-3.3V | 2 | 2-input multiplexer |
Logic density map
Logic cells per mm² in each 0.1 mm square of the block (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (32k logic cells per mm²), found by sliding a 0.1 mm square over the block in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.
Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.