wafer.space Run 1

TillitisZedulo-testchip2025

TZ01 · Memory test chip · 1 × 1 slot

Layout render of TillitisZedulo-testchip2025

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		4k (6% of buffer maximum)
over the 12.92 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		3k
over all 19.65 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²		18k (24% of buffer maximum)
Core covered by logic13%
Transistor density
transistors per mm²		156k average, 261k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

eFUSE and SRAM testchip put together by Egorexe and Zedulo team with support from Tillitis

Source repository

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.92 mm² inside the pad ring
as set in the design's own layout settings
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements2 on the reticle, in slots A3, B3 TZ01 on the reticle
Bond pads74
Transistors2,014,212
Logic cells58,018 + 228,360 filler and tap cells
Libraries 7t-5V (58k)
SRAM8 macros, 24,064 bits

Submission

LicenceApache-2.0 declared
Repository: Apache-2.0 in LICENSE — agrees
Templatewafer-space/gf180mcu-project-template 1.3.1 or 1.3.2
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit 1d1f91d4f362.The template releases named above are the ones whose Makefile pins the same PDK as that commit (PDK_TAG 1.6.4).
Chip-on-boardNot selected at submission
PrecheckPassed the check it was accepted on, 2025-12-15
Passed latest re-run, 2026-08-03, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells, fd SRAM, 47,064 custom transistors
6 V44 custom transistors
Gate oxidesThick only (5 V/6 V) in the design itself
MIM capacitors9 (900 µm², between Metal4 and Metal5)
all in reused simple_por
High-resistance poly resistors88 (2,200 µm²)
all in reused simple_por
eFuses2,424 (417,153 µm²)
I/O librarygf180mcu_fd_io (1122 cells), gf180mcu_ws_io (18 cells)

Where the area went

How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.

9%
26%
23%
36%
  • Logic cells 1.73 mm² (9%)
  • SRAM 1.41 mm² (7%)
  • Filler and tap cells 5.20 mm² (26%)
  • Other 4.58 mm² (23%)
  • Pad ring 7.20 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
buf_27t-5V 7,472Buffer (2x drive)
nand2_17t-5V 6,5912-input NAND gate
dffq_17t-5V 4,796D flip-flop (1 bit storage)
oai21_17t-5V 4,150OR-AND-Invert compound gate
aoi21_17t-5V 3,218AND-OR-Invert compound gate
nor2_17t-5V 3,0702-input NOR gate
clkinv_17t-5V 2,607Clock inverter
dffrnq_17t-5V 2,495D flip-flop with reset
clkbuf_17t-5V 2,331Clock buffer
mux2_27t-5V 2,1412-input multiplexer (2x drive)

Logic density map

147 logic cells, 54,812 transistors, 16% SRAM 549 logic cells, 104,384 transistors, 41% SRAM 7,387 logic cells, 135,018 transistors, 15% SRAM 1,458 logic cells, 59,777 transistors 3,851 logic cells, 86,820 transistors, 3% SRAM 10,487 logic cells, 166,473 transistors, 7% SRAM 12,067 logic cells, 173,016 transistors, 2% SRAM 2,659 logic cells, 86,364 transistors 230 logic cells, 39,170 transistors 1,734 logic cells, 64,466 transistors 2,466 logic cells, 64,628 transistors 491 logic cells, 51,151 transistors 4,641 logic cells, 127,512 transistors 3,137 logic cells, 180,653 transistors 2,418 logic cells, 167,290 transistors 1,224 logic cells, 75,200 transistors 1,464 logic cells, 64,189 transistors, 10% SRAM 1,554 logic cells, 114,631 transistors, 26% SRAM 14 logic cells, 135,247 transistors, 21% SRAM 40 logic cells, 62,565 transistors 0 logic cells, 176 transistors 0 logic cells, 256 transistors 0 logic cells, 255 transistors 0 logic cells, 159 transistors gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram128x8m8wm1 gf180mcu_fd_ip_sram__sram256x8m8wm1 gf180mcu_fd_ip_sram__sram64x8m8wm1 Densest SRAM-free mm²: 18,145 logic cells <1k 1k 7k 1k 4k 10k 12k 3k <1k 2k 2k <1k 5k 3k 2k 1k 1k 2k <1k <1k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (18k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

SRAM macros

The ready-made memory blocks this design uses.

MacroCountBits each
gf180mcu_fd_ip_sram__sram128x8m8wm11 1,024
gf180mcu_fd_ip_sram__sram256x8m8wm11 2,048
gf180mcu_fd_ip_sram__sram512x8m8wm15 4,096
gf180mcu_fd_ip_sram__sram64x8m8wm11 512

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. TZ01 was accepted on this check, and has been checked again since with newer rules.

All 15 steps passed, with 0 KLayout DRC errors, on 2025-12-15.

Every step, and the latest re-run
StepAccepted on
check 105, 2025-12-15, initial		Latest re-run
check 774, 2026-08-03, drc_update, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Rendernot in this flowpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCpassedpassed
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)00
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

Want a chip of your own like this one?

wafer.space Run 3 takes orders until 9 December 2026. Or start smaller with Tiny Tapeout: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3.

Reserve a slot
Start with Tiny Tapeout
← TTPG Tiny Tapeout GF 0.2, power-gated All projects wafer.space Logo WSLG →