Tiny Tapeout GF 0.2 · Die TTP2 on wafer.space Run 1: the standard edition

2048 sliding tile puzzle game (VGA)

194 · Games · 2 × 2 tiles

by Uri Shaked

Layout render of 2048 sliding tile puzzle game (VGA)

Rendered from the layout at 0.44 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		20k (26% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		38k (50% of buffer maximum)
Core covered by logic54%
Transistor density
transistors per mm²		284k average, 322k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Slide numbered tiles on a grid to combine them to create a tile with the number 2048.

Source repository Its page on Tiny TapeoutBuy this chip

Size711 × 325 µm (0.231 mm²)
Macrott_um_2048_vga_game
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles2 × 2 at column 5, row 7 of the tile grid
Mux address194
LanguageVerilog
Clock25.175 MHz
Built withLibreLane 2.4.2, open_pdks 0fe599b2afb6
Transistors66,457
Logic cells4,680 + 6,375 filler and tap cells
Libraries 7t-5V (5k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

54%
42%
  • Logic cells 0.13 mm² (54%)
  • Filler and tap cells 0.10 mm² (42%)
  • Other 0.01 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 5592-input NAND gate
oai21_17t-5V 309OR-AND-Invert compound gate
dffq_17t-5V 298D flip-flop (1 bit storage)
nor2_17t-5V 2612-input NOR gate
aoi21_17t-5V 255AND-OR-Invert compound gate
clkinv_17t-5V 166Clock inverter
buf_27t-5V 141Buffer (2x drive)
nand2_27t-5V 1402-input NAND gate (2x drive)
nand3_17t-5V 1353-input NAND gate
oai211_17t-5V 133OR-AND-Invert compound gate

Logic density map

148 logic cells, 2,732 transistors 202 logic cells, 2,845 transistors 157 logic cells, 2,637 transistors 308 logic cells, 3,189 transistors 281 logic cells, 3,046 transistors 139 logic cells, 2,599 transistors 0 logic cells, 2,129 transistors 0 logic cells, 147 transistors 261 logic cells, 3,574 transistors 361 logic cells, 3,417 transistors 287 logic cells, 3,322 transistors 279 logic cells, 3,075 transistors 261 logic cells, 2,971 transistors 176 logic cells, 2,738 transistors 0 logic cells, 2,219 transistors 0 logic cells, 153 transistors 277 logic cells, 3,169 transistors 312 logic cells, 3,288 transistors 309 logic cells, 3,358 transistors 286 logic cells, 3,366 transistors 271 logic cells, 3,183 transistors 97 logic cells, 2,608 transistors 0 logic cells, 2,218 transistors 0 logic cells, 153 transistors 12 logic cells, 488 transistors 59 logic cells, 696 transistors 66 logic cells, 753 transistors 56 logic cells, 682 transistors 45 logic cells, 606 transistors 30 logic cells, 587 transistors 0 logic cells, 476 transistors 0 logic cells, 33 transistors Densest SRAM-free 0.1 mm square: 381 logic cells 15k 20k 16k 31k 28k 14k 0 26k 36k 29k 28k 26k 18k 0 28k 31k 31k 29k 27k 10k 0

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (38k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

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Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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