Tiny Tapeout GF 0.2 · Die TTP2 on wafer.space Run 1: the standard edition

VGA Drop (audio/visual demo)

134 · Retro computing · 2 × 2 tiles

by ReJ aka Renaldas Zioma, eriQue aka Erik Hemming, Matthias Kampa

Layout render of VGA Drop (audio/visual demo)

Rendered from the layout at 0.44 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		15k (26% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		27k (46% of buffer maximum)
Core covered by logic45%
Transistor density
transistors per mm²		204k average, 235k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Tiny 8 part Megademo! TBL^Nesnausk^SonikClique

Source repository Its page on Tiny TapeoutBuy this chip

Size711 × 325 µm (0.231 mm²)
Macrott_um_rejunity_vga_test01
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles2 × 2 at column 0, row 7 of the tile grid
Mux address134
LanguageVerilog
Clock25.175 MHz
Built withLibreLane 2.4.2, open_pdks 0fe599b2afb6
Transistors47,884
Logic cells3,625 + 5,988 filler and tap cells
Libraries 9t-5V (4k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V9t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

45%
49%
  • Logic cells 0.10 mm² (45%)
  • Filler and tap cells 0.12 mm² (49%)
  • Other 0.01 mm² (6%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_19t-5V 6942-input NAND gate
nor2_19t-5V 3212-input NOR gate
xnor2_19t-5V 3102-input XNOR gate
oai21_19t-5V 211OR-AND-Invert compound gate
aoi21_19t-5V 208AND-OR-Invert compound gate
xor2_19t-5V 1962-input XOR gate
clkinv_19t-5V 179Clock inverter
dffq_19t-5V 136D flip-flop (1 bit storage)
xnor3_19t-5V 115
and2_19t-5V 1072-input AND gate

Logic density map

78 logic cells, 1,794 transistors 216 logic cells, 2,218 transistors 196 logic cells, 2,280 transistors 197 logic cells, 2,267 transistors 210 logic cells, 2,127 transistors 137 logic cells, 2,004 transistors 5 logic cells, 1,684 transistors 0 logic cells, 114 transistors 179 logic cells, 2,112 transistors 251 logic cells, 2,425 transistors 245 logic cells, 2,368 transistors 206 logic cells, 2,432 transistors 244 logic cells, 2,276 transistors 244 logic cells, 2,335 transistors 63 logic cells, 1,819 transistors 0 logic cells, 117 transistors 192 logic cells, 2,220 transistors 217 logic cells, 2,412 transistors 258 logic cells, 2,387 transistors 215 logic cells, 2,330 transistors 186 logic cells, 2,095 transistors 42 logic cells, 1,893 transistors 0 logic cells, 1,740 transistors 0 logic cells, 120 transistors 1 logic cells, 281 transistors 14 logic cells, 383 transistors 26 logic cells, 392 transistors 3 logic cells, 338 transistors 0 logic cells, 297 transistors 0 logic cells, 302 transistors 0 logic cells, 301 transistors 0 logic cells, 21 transistors Densest SRAM-free 0.1 mm square: 272 logic cells 8k 22k 20k 20k 21k 14k <1k 18k 25k 24k 21k 24k 24k 6k 19k 22k 26k 21k 19k 4k 0

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (27k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project
Buy this chip

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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