Tiny Tapeout GF 0.2 · Die TTP2 on wafer.space Run 1: the standard edition

Wildcat RISC-V

038 · RISC-V and CPUs · 3 × 2 tiles

by Martin Schoeberl

Layout render of Wildcat RISC-V

Rendered from the layout at 0.67 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		16k (22% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		34k (45% of buffer maximum)
Core covered by logic48%
Transistor density
transistors per mm²		276k average, 311k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Wildcat: a 3-stage RISC-V implementation

Source repository Its page on Tiny TapeoutBuy this chip

Size1076 × 325 µm (0.350 mm²)
Macrott_um_schoeberl_wildcat
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles3 × 2 at column 0, row 10 of the tile grid
Mux address38
LanguageChisel
Clock25 MHz
Built withLibreLane 3.0.0.dev45, open_pdks 8afc8346a57f
Transistors98,496
Logic cells5,867 + 11,364 filler and tap cells
Libraries 7t-5V (6k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

48%
47%
  • Logic cells 0.17 mm² (48%)
  • Filler and tap cells 0.17 mm² (47%)
  • Other 0.02 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 9112-input NAND gate
oai21_17t-5V 662OR-AND-Invert compound gate
dffq_17t-5V 415D flip-flop (1 bit storage)
dffq_47t-5V 392D flip-flop (1 bit storage, 4x drive)
buf_47t-5V 351Buffer (4x drive)
nor2_17t-5V 3382-input NOR gate
aoi21_17t-5V 270AND-OR-Invert compound gate
mux2_27t-5V 2372-input multiplexer (2x drive)
inv_17t-5V 219Inverter
buf_27t-5V 164Buffer (2x drive)

Logic density map

28 logic cells, 2,115 transistors 134 logic cells, 2,635 transistors 186 logic cells, 2,733 transistors 220 logic cells, 2,959 transistors 208 logic cells, 2,890 transistors 193 logic cells, 2,887 transistors 172 logic cells, 2,846 transistors 153 logic cells, 2,785 transistors 120 logic cells, 2,607 transistors 30 logic cells, 2,250 transistors 0 logic cells, 1,470 transistors 56 logic cells, 2,386 transistors 234 logic cells, 3,126 transistors 222 logic cells, 3,269 transistors 223 logic cells, 3,400 transistors 270 logic cells, 3,321 transistors 237 logic cells, 3,284 transistors 242 logic cells, 3,258 transistors 250 logic cells, 3,205 transistors 150 logic cells, 2,772 transistors 10 logic cells, 2,254 transistors 0 logic cells, 1,530 transistors 143 logic cells, 2,853 transistors 189 logic cells, 3,106 transistors 207 logic cells, 3,198 transistors 251 logic cells, 3,352 transistors 243 logic cells, 3,212 transistors 269 logic cells, 3,365 transistors 273 logic cells, 3,350 transistors 323 logic cells, 3,099 transistors 308 logic cells, 3,081 transistors 57 logic cells, 2,358 transistors 0 logic cells, 1,530 transistors 21 logic cells, 534 transistors 24 logic cells, 553 transistors 13 logic cells, 530 transistors 36 logic cells, 649 transistors 37 logic cells, 673 transistors 27 logic cells, 632 transistors 38 logic cells, 550 transistors 45 logic cells, 575 transistors 25 logic cells, 510 transistors 0 logic cells, 474 transistors 0 logic cells, 330 transistors Densest SRAM-free 0.1 mm square: 339 logic cells 3k 13k 19k 22k 21k 19k 17k 15k 12k 3k 0 6k 23k 22k 22k 27k 24k 24k 25k 15k 1k 0 14k 19k 21k 25k 24k 27k 27k 32k 31k 6k 0

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (34k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project
Buy this chip

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

← 033 wafer.space Logo VGA Screensaver All projects TinyQV RISC-V SoC 039 →