SRAMs on Open Source Silicon#

In November 2022, three months after the GF180MCU PDK was made open source, someone on the open source silicon forum posted a complaint:

Holy cow, these gf180 SRAM are huge compared to the sky130 ones.

They weren’t kidding: GF180MCU’s 256x8 SRAM was ~4x bigger than SKY130’s 256x32 and manages to store less. It’s no good for people with limited silicon area to build in.

Tim Edwards – the writer of Magic and Netgen, core components of the modern open source ASIC flow – replied:

Note that this is a 5V SRAM. All of our IP for GF180MCU is for 5V operation.

And that was it… for a while at least. Luckily, there’s been some advancements recently. So let’s skip a few years (and a defunct company) ahead to present day and see what has changed.

Existing Options#

The only SRAMs available for the GF180MCU process were Global Foundries’ own 5 V macros - they were large and severely impeded the space you had left for your project, but what else could you do? After the shutting down of eFabless and with Google stopping their GFMPW runs, there was no incentive to improve them - why bother if they wouldn’t get taped out? Now with wafer.space, that changes – GF180MCU is back on the table.

Edwards knew that the GF180MCU PDK desperately needed a 3.3 V library, but with Tholin already working on a cell library, he turned his attention back to the very thing diagnosed back in 2022.

Shrinking It Down#

Set on creating a 3.3 V capable SRAM, Edwards began by looking at the 256 B macro for arbitrary reasons. He describes his approach as a “hack”, but it’s a pretty clever approach to reusing components that were available:

1. Design a core cell for the 3.3 V devices based on the GF-provided SRAM rules (that are publicly available)
2. Determine the size difference between a 3.3 V core cell to the existing 5 V core cell
3. Import the 5 V SRAM with the scaling determined by the previous step - the X and Y scales were different, making it slightly tricky
4. Re-import the individual devices scaled by the width/length difference between minimum-length 5 V devices and minimum-length 3.3 V devices
5. Clean up the resulting mess

After a week of hard work, he had his first layout ready, and the process nailed down for porting the rest of the macros. For the others, he manipulated the height of the block and added in extra rows where necessary. Original netlists were converted using a quick Python script and cleaned up by hand. He even created XSchem schematics which had been missing in the PDK, making it a very valuable addition to the library.

Provider	Macro	Voltage	Capacity (B)	Area (µm²)
GlobalFoundries	gf180mcu_fd_ip_sram__sram128x8m8wm1	5 V	128	116118.5168
GlobalFoundries	gf180mcu_fd_ip_sram__sram256x8m8wm1	5 V	256	147212.4368
GlobalFoundries	gf180mcu_fd_ip_sram__sram512x8m8wm1	5 V	512	209400.2768
Tim Edwards	gf180mcu_ocd_ip_sram__sram64x8m8wm1	3 V	64	45860.873
Tim Edwards	gf180mcu_ocd_ip_sram__sram256x8m8wm1	3 V	256	67771.406
Tim Edwards	gf180mcu_ocd_ip_sram__sram512x8m8wm1	3 V	512	96985.461
Tim Edwards	gf180mcu_ocd_ip_sram__sram1024x8m8wm1	3 V	1024	155413.547

Edwards compared the two devices together, saying that his 3.3 V SRAM takes up half the area of the 5 V SRAM – wonderful news to anyone who was wanting to include an SRAM block in their design. He goes further to say that “it [the 5 V SRAM] makes the process more like a 0.5µm process than a 0.18µm process. The 3.3 V devices are also large but makes it more like a 0.25µm process.”.

An Extra Bit?#

During his exploration of the foundry-provided SRAM, he noticed that the decoder circuitry went up to 10 bits, yet Global Foundries only ever utilized 9 bits – their largest macro maxed out at a depth of 512 B.

There isn’t a clear reason as to why they didn’t provide a 1 KiB macro – perhaps it didn’t meet their requirements, or maybe they just put in the extra bit because they could? It’s all speculation, but the most important part is that Edwards took the liberty of creating the 1 KiB macro that had originally been missing.

Unfortunately, for any larger sizes, considerable work would have to be done on the decoder circuitry as his “hack” method would no longer work.

Testing & Results#

These shrunk down SRAMs are expected to be faster because they’re using thinner oxide devices, despite the fact that it’s using the same SRAM core cells as the 5 V macros.

An initial version was taped out on Run #1, and some preliminary testing was done just in time to tell everyone that his work was functional and operating to at least 100 MHz before Run #2 closed.

Unfortunately due to some delivery snags, Edwards wasn’t able to get his hands on the extra logic analyzer he would’ve needed to complete an exhaustive test of the SRAMs, but his testing was good enough to call the part functional.

Characterization still remains to be done, but his work has advanced the GF180MCU PDK and provided the community with memory that they can use to build their projects with.

Memory Generators#

A different approach to getting memory on silicon is by using a generator. Thanks to the regular structure of a memory component, macros can be built algorithmically and without tedious hours of manual work.

A benefit of having a memory generator available is that you, as the user, can decide precisely how large you want the memory block to be. This allows you to optimize your area usage without wasting precious silicon on memory that sits unused.

Staf Verhaegen, of Chips4Makers, ported his flexmem SRAM generator to use the GF180MCU PDK and has taped out a handful of test chips on Run #2. They’re still in production, so there’s no test data or characterization yet.

If you’d like to stay up to date, consider joining the wafer.space Discord or chatting to us on Matrix.

Get Started Today#

Run #3 is in full swing at the moment, so don’t miss your opportunity to tape out. You’ve got until 9 December 2026 to purchase a slot, and the submission deadline a week after on 16 December 2026.

Read more on our Crowd Supply page, jump in with our project template and join our community Discord to chat to other designers and get help.