Die sort report · run2

Every die of run2's wafers, picked off the wafer and placed into tape-and-reel, 2026-10-16 to 2026-10-25. Made 2026-11-03. Laid out in unload order: the order the dies come off each reel, last placed first.

wafer.space GF180MCU Run 2 · Find your project · Data and notes: wafer-space/ws-run2-pickmap on GitHub

Dies in tape

11,449

98.3% of 11,652 mapped

Good

10,771

92.4% of mapped

Flipped

239

on 8 reels, wafer1 & wafer2 & wafer4

Lost

203

1.7% of mapped

Wafers

2026-10-16 to 2026-10-25

Cycle time

16 s

median per die, 63 h of placing

How each die ended up

Each die has one status. The machine photographed every die in its pocket and checked the photo; the ones it was unsure of were looked at by a person.

Status	Dies	Means
✓ Good	10,771	In its pocket, face up, the right way round: the pocket check passed it, or a person looked and vouched for it.
? Placed, unverified	350	In tape, but the automatic pocket check did not pass it (or did not run) and nobody has looked since.
! Placed, suspect	89	In tape, but a person reviewing its photo said it was not seated, the pocket looked empty, or it was unclear.
↻ Flipped	239	In tape the wrong way round - turned 180 degrees (or 90) from the reel's orientation.
× Lost	203	Not in tape: missed or dropped on the way, taken back out, or gone from the wafer before it could be picked.

By wafer

Wafer maps

Every die where it sat on the wafer, coloured by how it ended up. Hover a die for its project, reel and place on the reel.

Flipped dies

239 dies went into tape turned the wrong way round. They are listed here by wafer and reel, with their place on the reel (die number off the reel: #1 is the first die off, the last run2 die placed on it). The full list is flipped.csv, and each die is in exceptions.csv.

Wafer	Reel	Project	Flipped	How	Where off the reel (die #)	Seen in
wafer1	reticle S-2_-2	45 projects, one reticle	45	FLIPPED_180 27, ROTATED_90 18	10-54	angles
wafer1	reticle S-3_-1	53 projects, one reticle	53	FLIPPED_180 35, ROTATED_90 18	1-53	angles
wafer2	AS04	AS04 Multi-Project die using 3.3V SCL	1	ROTATED_90 1	175	angles
wafer2	SCC0	Private	1	ROTATED_90 1	157	angles
wafer4	APTX	Private	38	FLIPPED_180 38	77-114	photo
wafer4	COLF	Private	37	FLIPPED_180 37	77-113	photo
wafer4	NEXA	Private	36	FLIPPED_180 36	73-108	photo
wafer4	WSLG	Wafer.Space Logo	28	ROTATED_90 1, FLIPPED_180 27	75-102	photo

Reels

59 reels: one per project code. This package shows them in the order they come off - the reverse of the order they went on: the last die placed is the first off, so each reel starts with wafer6 and ends with wafer1. Pick a project to see its reel up close, a row per wafer, each die numbered by its place off the reel.

Show one project

Reel	Project	Slot	Dies	Pockets (est.)	Flipped	Flipped die #	Wafers, by die # off the reel
0000	ICELab Test Chip	1x0p5	216	216	0		wafer6 1-37; wafer5 38-73; wafer4 74-110; wafer3 111-147; wafer2 148-183; wafer1 184-216
AMM1_1	raybox-zero wafer.space run 2 half height	1x0p5	205	205	0		wafer6 1-35; wafer5 36-70; wafer4 71-105; wafer3 106-140; wafer2 141-173; wafer1 174-205
AMM1_2	raybox-zero wafer.space run 2 half height	1x0p5	216	216	0		wafer6 1-37; wafer5 38-74; wafer4 75-110; wafer3 111-147; wafer2 148-182; wafer1 183-216
APTX	Private	1x1	223	223	38	77-114	wafer6 1-38; wafer5 39-76; wafer4 77-114; wafer3 115-152; wafer2 153-189; wafer1 190-223
AS04	AS04 Multi-Project die using 3.3V SCL	1x1	209	209	1	175	wafer6 1-36; wafer5 37-72; wafer4 73-108; wafer3 109-144; wafer2 145-179; wafer1 180-209
AS16	AS16 CPU	1x0p5	199	217	0		wafer6 1-34; wafer5 35-68; wafer4 69-102; wafer3 103-136; wafer2 137-169; wafer1 170-199
BTX1	BTX	1x1	189	207	0		wafer6 1-34; wafer5 35-68; wafer4 69-102; wafer3 103-136; wafer2 137-158; wafer1 159-189
CAB1	Cabrera CoB	1x0p5	212	230	0		wafer6 1-36; wafer5 37-72; wafer4 73-108; wafer3 109-144; wafer2 145-179; wafer1 180-212
CAFE	Expresso Ethernet Chip: 100Mbps Ethernet switch + Heat death of the Universe Beacon - 0.5x0.5 version - Preferred version	0p5x0p5	211	229	0		wafer6 1-36; wafer5 37-72; wafer4 73-108; wafer3 109-142; wafer2 143-178; wafer1 179-211
CLON	Cloneless2	1x1	212	230	0		wafer6 1-36; wafer5 37-72; wafer4 73-108; wafer3 109-144; wafer2 145-179; wafer1 180-212
COLF	Private	1x1	221	221	37	77-113	wafer6 1-38; wafer5 39-76; wafer4 77-113; wafer3 114-151; wafer2 152-186; wafer1 187-221
CRD2	Private	1x0p5	212	212	0		wafer6 1-36; wafer5 37-72; wafer4 73-108; wafer3 109-144; wafer2 145-179; wafer1 180-212
CSC1	Private	1x0p5	211	211	0		wafer6 1-36; wafer5 37-71; wafer4 72-106; wafer3 107-142; wafer2 143-178; wafer1 179-211
DCO0	Standard Cell DCO+TDC	1x0p5	202	220	0		wafer6 1-31; wafer5 32-66; wafer4 67-101; wafer3 102-136; wafer2 137-170; wafer1 171-201; wafer6 202-202
DPK1	bio180	0p5x1	210	210	0		wafer6 1-36; wafer5 37-70; wafer4 71-106; wafer3 107-142; wafer2 143-177; wafer1 178-210
DPK2	cordic-romless-x8	0p5x0p5	205	223	0		wafer6 1-35; wafer5 36-70; wafer4 71-105; wafer3 106-140; wafer2 141-175; wafer1 176-205
EURO	EuroSynth	1x0p5	202	220	0		wafer6 1-35; wafer5 36-70; wafer4 71-105; wafer3 106-140; wafer2 141-170; wafer1 171-202
FC01	Flip Chip pad test version 1	0p5x0p5	210	210	0		wafer6 1-34; wafer5 35-69; wafer4 70-104; wafer3 105-141; wafer2 142-177; wafer1 178-210
FS01	Test chip with 3.3V SRAM blocks using regular design rules	0p5x1	205	205	0		wafer6 1-35; wafer5 36-69; wafer4 70-104; wafer3 105-139; wafer2 140-173; wafer1 174-205
FS02	Test chip with 3.3V SRAM blocks using SRAM design rules	0p5x1	213	213	0		wafer6 1-36; wafer5 37-72; wafer4 73-108; wafer3 109-144; wafer2 145-180; wafer1 181-213
FS03	Test chip with 5V SRAM blocks	0p5x1	209	209	0		wafer6 1-34; wafer5 35-69; wafer4 70-104; wafer3 105-140; wafer2 141-176; wafer1 177-209
GD04_1	Racquet Wide 1x0.5	1x0p5	218	218	0		wafer6 1-37; wafer5 38-73; wafer4 74-110; wafer3 111-147; wafer2 148-183; wafer1 184-218
GD04_2	Racquet Wide 1x0.5	1x0p5	209	209	0		wafer6 1-34; wafer5 35-70; wafer4 71-105; wafer3 106-141; wafer2 142-177; wafer1 178-209
HZ80	FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 1 slot)	0p5x1	206	206	0		wafer6 1-35; wafer5 36-69; wafer4 70-104; wafer3 105-139; wafer2 140-174; wafer1 175-206
ISHI	ISHI-KAI_Multiple_Projects_WaferSapce-GF180-2	0p5x1	211	211	0		wafer6 1-36; wafer5 37-72; wafer4 73-107; wafer3 108-143; wafer2 144-178; wafer1 179-211
KIAN	KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU Run 2	1x1	210	228	0		wafer6 1-36; wafer5 37-72; wafer4 73-108; wafer3 109-143; wafer2 144-177; wafer1 178-210
MEME_1	Artwork Meme Chip	1x0p5	223	223	0		wafer6 1-38; wafer5 39-75; wafer4 76-113; wafer3 114-151; wafer2 152-187; wafer1 188-223
MEME_2	Artwork Meme Chip	1x0p5	219	219	0		wafer6 1-37; wafer5 38-74; wafer4 75-111; wafer3 112-148; wafer2 149-185; wafer1 186-219
MOLE	FABulous FPGA	1x1	209	227	0		wafer6 1-36; wafer5 37-71; wafer4 72-107; wafer3 108-143; wafer2 144-177; wafer1 178-209
NAX1	Naxos CoB	1x0p5	212	230	0		wafer6 1-36; wafer5 37-72; wafer4 73-108; wafer3 109-144; wafer2 145-179; wafer1 180-212
NEXA	Private	1x1	213	213	36	73-108	wafer6 1-36; wafer5 37-72; wafer4 73-108; wafer3 109-144; wafer2 145-180; wafer1 181-213
NSCN	Private	1x0p5	210	213	0		wafer4 1-36; wafer6 37-71; wafer5 72-106; wafer3 107-142; wafer2 143-177; wafer1 178-210
OCD3	3.3V SRAM test 2	1x0p5	212	230	0		wafer6 1-36; wafer5 37-72; wafer4 73-108; wafer3 109-144; wafer2 145-179; wafer1 180-212
PSOC	Simplest possible PicoSoC implementation using wafer.space flow	1x0p5	223	223	0		wafer6 1-38; wafer5 39-75; wafer4 76-113; wafer3 114-151; wafer2 152-188; wafer1 189-223
QBNL	Private	1x1	210	210	0		wafer6 1-36; wafer5 37-72; wafer4 73-108; wafer3 109-144; wafer2 145-177; wafer1 178-210
QZ80	FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 0.5 slot)	0p5x0p5	205	223	0		wafer6 1-35; wafer5 36-69; wafer4 70-104; wafer3 105-139; wafer2 140-173; wafer1 174-205
RLCM	RLCM: Test Passives For GF180MCUD	0p5x1	205	205	0		wafer6 1-35; wafer5 36-69; wafer4 70-104; wafer3 105-139; wafer2 140-173; wafer1 174-205
SALU	Simple ALU	0p5x0p5	195	213	0		wafer6 1-34; wafer5 35-68; wafer4 69-98; wafer3 99-131; wafer2 132-164; wafer1 165-195
SCC0	Private	1x1	221	221	1	157	wafer6 1-38; wafer5 39-75; wafer4 76-113; wafer3 114-150; wafer2 151-186; wafer1 187-221
SCC1	Private	0p5x0p5	208	226	0		wafer6 1-34; wafer5 35-69; wafer4 70-105; wafer3 106-141; wafer2 142-176; wafer1 177-208
SCDO	Private	0p5x1	205	205	0		wafer6 1-35; wafer5 36-70; wafer4 71-105; wafer3 106-139; wafer2 140-173; wafer1 174-205
SCML	ML-Audio SC	1x1	222	240	0		wafer6 1-38; wafer5 39-76; wafer4 77-114; wafer3 115-151; wafer2 152-187; wafer1 188-222
SCMT	microTheia	1x1	205	223	0		wafer6 1-35; wafer5 36-70; wafer4 71-105; wafer3 106-140; wafer2 141-173; wafer1 174-205
SCTP	SlugTPU	1x1	205	223	0		wafer6 1-35; wafer5 36-69; wafer4 70-104; wafer3 105-139; wafer2 140-173; wafer1 174-205
SCUP	GF180MCU Peripherals	1x1	217	235	0		wafer6 1-37; wafer5 38-74; wafer4 75-111; wafer3 112-148; wafer2 149-183; wafer1 184-217
T0P3	Tiny Tapeout GF 0p3	1x1	212	230	0		wafer6 1-36; wafer5 37-72; wafer4 73-108; wafer3 109-144; wafer2 145-179; wafer1 180-212
T26A	Tiny Tapeout GF 26a	1x1	206	206	0		wafer6 1-35; wafer5 36-70; wafer4 71-105; wafer3 106-140; wafer2 141-174; wafer1 175-206
T26B	Tiny Tapeout GF 26b	1x1	211	211	0		wafer6 1-36; wafer5 37-72; wafer4 73-108; wafer3 109-144; wafer2 145-178; wafer1 179-211
TQVA	TinyQV - Crowdsourced Risc-V SoC	0p5x0p5	208	226	0		wafer6 1-34; wafer5 35-68; wafer4 69-104; wafer3 105-140; wafer2 141-175; wafer1 176-208
TQVC	TinyQV - Crowdsourced Risc-V SoC (1x0.5)	1x0p5	200	218	0		wafer6 1-34; wafer5 35-68; wafer4 69-102; wafer3 103-136; wafer2 137-169; wafer1 170-200
TQVD	TinyQV - RISC-V SoC with HDMI output	0p5x0p5	200	218	0		wafer6 1-32; wafer5 33-66; wafer4 67-100; wafer3 101-135; wafer2 136-168; wafer1 169-200
TQVE	TinyQV - RISC-V SoC with experimental pad setup	0p5x0p5	207	225	0		wafer6 1-35; wafer5 36-70; wafer4 71-105; wafer3 106-140; wafer2 141-175; wafer1 176-207
WSLG	Wafer.Space Logo	1x1	219	219	28	75-102	wafer6 1-37; wafer5 38-74; wafer4 75-111; wafer3 112-148; wafer2 149-185; wafer1 186-219
XQAC	Private	0p5x1	211	211	0		wafer6 1-36; wafer5 37-71; wafer4 72-107; wafer3 108-143; wafer2 144-178; wafer1 179-211
reticle S-2_-2	one-tape reticle reel	1x1 tape, mixed dies	54	54	45	10-54	wafer1 1-54
reticle S-3_-1	one-tape reticle reel	1x1 tape, mixed dies	53	53	53	1-53	wafer1 1-53
reticle S-3_-2	one-tape reticle reel	1x1 tape, mixed dies	1	1	0		wafer1 1-1
reticle S-3_-3	one-tape reticle reel	1x1 tape, mixed dies	1	1	0		wafer1 1-1
reticle S-3_0	one-tape reticle reel	1x1 tape, mixed dies	1	1	0		wafer1 1-1

Projects

54 project codes on the reticle. Counts are dies across all of run2's wafers. Click a code for that project's reel page.

Code	Project	Slot	Mapped	Good	Unverified	Suspect	Flipped	Lost	Good %
0000	ICELab Test Chip	1x0p5	222	215	1	0	2	4	96.9%
AMM1_1	raybox-zero wafer.space run 2 half height	1x0p5	210	199	6	0	2	3	94.8%
AMM1_2	raybox-zero wafer.space run 2 half height	1x0p5	222	214	2	0	2	4	96.4%
APTX	Private	1x1	228	180	0	5	40	3	79.0%
AS04	AS04 Multi-Project die using 3.3V SCL	1x1	216	198	0	13	3	2	91.7%
AS16	AS16 CPU	1x0p5	204	198	1	0	2	3	97.1%
BTX1	BTX	1x1	204	189	0	0	2	13	92.7%
CAB1	Cabrera CoB	1x0p5	216	209	3	0	2	2	96.8%
CAFE	Expresso Ethernet Chip: 100Mbps Ethernet switch + Heat death of the Universe Beacon - 0.5x0.5 version - Preferred version	0p5x0p5	216	207	5	0	1	3	95.8%
CLON	Cloneless2	1x1	216	212	0	0	2	2	98.2%
COLF	Private	1x1	228	182	0	2	39	5	79.8%
CRD2	Private	1x0p5	216	212	0	0	2	2	98.2%
CSC1	Private	1x0p5	216	210	1	0	2	3	97.2%
DCO0	Standard Cell DCO+TDC	1x0p5	210	196	6	0	2	6	93.3%
DPK1	bio180	0p5x1	216	209	0	1	2	4	96.8%
DPK2	cordic-romless-x8	0p5x0p5	210	199	7	0	1	3	94.8%
EURO	EuroSynth	1x0p5	210	202	0	0	2	6	96.2%
FC01	Flip Chip pad test version 1	0p5x0p5	222	181	30	0	1	10	81.5%
FS01	Test chip with 3.3V SRAM blocks using regular design rules	0p5x1	210	202	2	1	2	3	96.2%
FS02	Test chip with 3.3V SRAM blocks using SRAM design rules	0p5x1	216	202	6	5	2	1	93.5%
FS03	Test chip with 5V SRAM blocks	0p5x1	216	201	2	6	2	5	93.1%
GD04_1	Racquet Wide 1x0.5	1x0p5	222	213	5	0	2	2	96.0%
GD04_2	Racquet Wide 1x0.5	1x0p5	216	205	4	0	2	5	94.9%
HZ80	FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 1 slot)	0p5x1	210	194	5	7	2	2	92.4%
ISHI	ISHI-KAI_Multiple_Projects_WaferSapce-GF180-2	0p5x1	216	207	1	3	2	3	95.8%
KIAN	KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU Run 2	1x1	216	159	51	0	2	4	73.6%
MEME_1	Artwork Meme Chip	1x0p5	228	223	0	0	2	3	97.8%
MEME_2	Artwork Meme Chip	1x0p5	222	216	3	0	2	1	97.3%
MOLE	FABulous FPGA	1x1	216	181	28	0	2	5	83.8%
NAX1	Naxos CoB	1x0p5	216	212	0	0	2	2	98.2%
NEXA	Private	1x1	216	175	0	2	38	1	81.0%
NSCN	Private	1x0p5	216	204	6	0	2	4	94.4%
OCD3	3.3V SRAM test 2	1x0p5	216	211	1	0	2	2	97.7%
PSOC	Simplest possible PicoSoC implementation using wafer.space flow	1x0p5	228	223	0	0	2	3	97.8%
QBNL	Private	1x1	216	203	1	6	2	4	94.0%
QZ80	FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 0.5 slot)	0p5x0p5	210	188	18	0	1	3	89.5%
RLCM	RLCM: Test Passives For GF180MCUD	0p5x1	210	201	2	2	2	3	95.7%
SALU	Simple ALU	0p5x0p5	210	137	59	0	1	13	65.2%
SCC0	Private	1x1	228	216	0	4	3	5	94.7%
SCC1	Private	0p5x0p5	216	192	17	0	1	6	88.9%
SCDO	Private	0p5x1	210	202	0	3	2	3	96.2%
SCML	ML-Audio SC	1x1	228	220	2	0	2	4	96.5%
SCMT	microTheia	1x1	210	204	1	0	2	3	97.1%
SCTP	SlugTPU	1x1	210	204	1	0	2	3	97.1%
SCUP	GF180MCU Peripherals	1x1	222	215	2	0	2	3	96.9%
T0P3	Tiny Tapeout GF 0p3	1x1	216	208	4	0	2	2	96.3%
T26A	Tiny Tapeout GF 26a	1x1	210	204	0	2	2	2	97.1%
T26B	Tiny Tapeout GF 26b	1x1	216	206	0	5	2	3	95.4%
TQVA	TinyQV - Crowdsourced Risc-V SoC	0p5x0p5	216	195	14	0	1	6	90.3%
TQVC	TinyQV - Crowdsourced Risc-V SoC (1x0.5)	1x0p5	204	193	7	0	2	2	94.6%
TQVD	TinyQV - RISC-V SoC with HDMI output	0p5x0p5	210	176	25	0	0	9	83.8%
TQVE	TinyQV - RISC-V SoC with experimental pad setup	0p5x0p5	210	195	13	0	1	1	92.9%
WSLG	Wafer.Space Logo	1x1	222	180	0	11	30	1	81.1%
XQAC	Private	0p5x1	216	192	8	11	2	3	88.9%

Each project, in its pocket

One die per project as the feeder camera saw it, seated in the tape. Click a photo for the machine's own check of it - the outline it found and what it measured. Private projects are left out: a photo would show the layout they keep private.

0000 in its pocket — **0000** ICELab Test Chip
218 in tape, 215 good · wafer4 S-2_-3/C3R4

AMM1_1 in its pocket — **AMM1_1** raybox-zero wafer.space run 2 half height
207 in tape, 199 good · wafer5 S-3_-2/C1R3

AMM1_2 in its pocket — **AMM1_2** raybox-zero wafer.space run 2 half height
218 in tape, 214 good · wafer5 S-1_0/C2R3

AS04 in its pocket — **AS04** AS04 Multi-Project die using 3.3V SCL
214 in tape, 198 good · wafer1 S-1_-4/C5R0

AS16 in its pocket — **AS16** AS16 CPU
201 in tape, 198 good · wafer3 S0_-2/C0R4

BTX1 in its pocket — **BTX1** BTX
191 in tape, 189 good · wafer5 S-1_-1/C0R0

CAB1 in its pocket — **CAB1** Cabrera CoB
214 in tape, 209 good · wafer5 S0_-3/C2R5

CAFE in its pocket — **CAFE** Expresso Ethernet Chip: 100Mbps Ethernet switch + Heat death of the Universe Beacon - 0.5x0.5 version - Preferred version
213 in tape, 207 good · wafer1 S-2_-2/C6R4

CLON in its pocket — **CLON** Cloneless2
214 in tape, 212 good · wafer2 S1_-4/C1R0

DCO0 in its pocket — **DCO0** Standard Cell DCO+TDC
204 in tape, 196 good · wafer3 S-1_1/C0R3

DPK1 in its pocket — **DPK1** bio180
212 in tape, 209 good · wafer3 S1_-3/C6R2

DPK2 in its pocket — **DPK2** cordic-romless-x8
207 in tape, 199 good · wafer4 S-2_1/C7R4

EURO in its pocket — **EURO** EuroSynth
204 in tape, 202 good · wafer3 S-2_0/C1R4

FC01 in its pocket — **FC01** Flip Chip pad test version 1
212 in tape, 181 good · wafer6 S0_0/C6R3

FS01 in its pocket — **FS01** Test chip with 3.3V SRAM blocks using regular design rules
207 in tape, 202 good · wafer1 S1_-1/C8R0

FS02 in its pocket — **FS02** Test chip with 3.3V SRAM blocks using SRAM design rules
215 in tape, 202 good · wafer2 S2_1/C7R0

FS03 in its pocket — **FS03** Test chip with 5V SRAM blocks
211 in tape, 201 good · wafer2 S-3_-3/C6R0

GD04_1 in its pocket — **GD04_1** Racquet Wide 1x0.5
220 in tape, 213 good · wafer6 S-3_1/C4R4

GD04_2 in its pocket — **GD04_2** Racquet Wide 1x0.5
211 in tape, 205 good · wafer4 S-2_-3/C5R4

HZ80 in its pocket — **HZ80** FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 1 slot)
208 in tape, 194 good · wafer1 S0_-1/C6R1

ISHI in its pocket — **ISHI** ISHI-KAI_Multiple_Projects_WaferSapce-GF180-2
213 in tape, 207 good · wafer6 S1_-1/C7R2

KIAN in its pocket — **KIAN** KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU Run 2
212 in tape, 159 good · wafer4 S-3_-2/C2R0

MEME_1 in its pocket — **MEME_1** Artwork Meme Chip
225 in tape, 223 good · wafer4 S-1_-3/C4R3

MEME_2 in its pocket — **MEME_2** Artwork Meme Chip
221 in tape, 216 good · wafer3 S1_1/C5R3

MOLE in its pocket — **MOLE** FABulous FPGA
211 in tape, 181 good · wafer5 S0_-1/C4R0

NAX1 in its pocket — **NAX1** Naxos CoB
214 in tape, 212 good · wafer6 S-3_0/C1R5

OCD3 in its pocket — **OCD3** 3.3V SRAM test 2
214 in tape, 211 good · wafer4 S-1_1/C2R4

PSOC in its pocket — **PSOC** Simplest possible PicoSoC implementation using wafer.space flow
225 in tape, 223 good · wafer2 S0_-3/C3R3

QZ80 in its pocket — **QZ80** FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 0.5 slot)
207 in tape, 188 good · wafer1 S-2_-2/C8R3

RLCM in its pocket — **RLCM** RLCM: Test Passives For GF180MCUD
207 in tape, 201 good · wafer3 S0_-4/C8R1

SALU in its pocket — **SALU** Simple ALU
197 in tape, 137 good · wafer1 S-3_-3/C7R3

SCML in its pocket — **SCML** ML-Audio SC
224 in tape, 220 good · wafer3 S2_0/C3R1

SCMT in its pocket — **SCMT** microTheia
207 in tape, 204 good · wafer3 S-3_0/C1R1

SCTP in its pocket — **SCTP** SlugTPU
207 in tape, 204 good · wafer5 S1_-4/C0R1

SCUP in its pocket — **SCUP** GF180MCU Peripherals
219 in tape, 215 good · wafer4 S-2_0/C2R1

T0P3 in its pocket — **T0P3** Tiny Tapeout GF 0p3
214 in tape, 208 good · wafer5 S0_1/C3R0

T26A in its pocket — **T26A** Tiny Tapeout GF 26a
208 in tape, 204 good · wafer3 S-3_0/C0R2

T26B in its pocket — **T26B** Tiny Tapeout GF 26b
213 in tape, 206 good · wafer2 S-1_-2/C1R2

TQVA in its pocket — **TQVA** TinyQV - Crowdsourced Risc-V SoC
210 in tape, 195 good · wafer5 S-2_1/C7R5

TQVC in its pocket — **TQVC** TinyQV - Crowdsourced Risc-V SoC (1x0.5)
202 in tape, 193 good · wafer5 S-2_1/C0R5

TQVD in its pocket — **TQVD** TinyQV - RISC-V SoC with HDMI output
201 in tape, 176 good · wafer4 S-1_2/C8R5

TQVE in its pocket — **TQVE** TinyQV - RISC-V SoC with experimental pad setup
209 in tape, 195 good · wafer5 S-2_-1/C8R4

WSLG in its pocket — **WSLG** Wafer.Space Logo
221 in tape, 180 good · wafer6 S-3_1/C5R1

The reticle

How the dies were sorted

1 · PickPins push the die up from below the wafer tape while the nozzle lifts it off.

2 · AlignAn up-looking camera sees the die on the nozzle and turns and centres it.

3 · PlaceA down-looking camera finds the pocket in the carrier tape and the die goes into it.

4 · CheckThe pocket is photographed and checked - size, position, flatness, turn - before the next die. Anything doubtful stops for a person.

Where the time went

Wafer	Mapped	Good	Unverified	Suspect	Flipped	Lost	Good %	Hours placing	First placed	Last placed
wafer1	1,942	1,712	35	33	98	64	88.2%	11.8	2026-10-16 14:27:16	2026-10-24 19:00:53
wafer2	1,942	1,803	38	25	2	74	92.8%	11.2	2026-10-17 17:28:18	2026-10-24 21:04:32
wafer3	1,942	1,866	49	19	0	8	96.1%	10.0	2026-10-18 12:43:34	2026-10-24 23:12:35
wafer4	1,942	1,728	56	5	139	14	89.0%	10.1	2026-10-18 16:46:36	2026-10-25 01:20:39
wafer5	1,942	1,862	54	2	0	24	95.9%	10.0	2026-10-18 20:41:14	2026-10-25 03:08:44
wafer6	1,942	1,800	118	5	0	19	92.7%	9.7	2026-10-18 22:38:50	2026-10-25 05:14:46

Lost dies

The data

Everything on this page, as files for other tools. The CSVs are UTF-8 with a header row; times are local, YYYY-MM-DD HH:MM:SS.

run2.xlsx		every table below as a sheet - open in Excel or import to Google Sheets
data/dies.csv		one row per die (11,652 rows) - the master table
data/reels.csv		one row per reel: dies, flipped die numbers, which wafer filled which part
data/reel_segments.csv		each unbroken run of one wafer's dies on a reel
data/flipped.csv		flipped dies by wafer and reel
data/exceptions.csv		every die that is not GOOD
data/projects.csv		per project: mapped, in tape, good
data/wafers.csv		per wafer
data/statuses.csv		what each status means
data/schema.csv		what every column means
svg/		every chart on this page as its own SVG
print/		a printable page per project reel, in the order the dies come off: its wafers and dies, the reel chart, every pocket