Reel TQVE

TinyQV - RISC-V SoC with experimental pad setup · die sort run2 · made 2026-11-03

TQVE in its pocket
TQVE in its pocket
ReelTQVE
ProjectTQVE - TinyQV - RISC-V SoC with experimental pad setup
Die size0p5x0p5 (width x height, of a 4.0 x 5.18 mm slot)
Batchrun2
Die orderAs it comes off: #1 is the first die off, the last one placed
Dies on the reel207, in 225 pockets (est.)
Empty pockets18, logged by the machine between wafers
Flipped, die #none
Suspect, die #none
Unverified, die #16, 22, 29, 40, 43-44, 87, 117, 119, 125, 149, 171, 184
Lost, not on the reel1 of this project's dies (dropped, missed or taken back out)

Wafer by wafer

WaferDie #Pockets (est.)Dies GoodUnverifiedSuspectFlipped Empty beforePlaced
wafer61-354-383532332026-10-23 21:40 - 21:52
wafer536-7042-763532332026-10-23 19:28 - 19:37
wafer471-10580-1143534132026-10-23 17:27 - 17:38
wafer3106-140118-1523532332026-10-23 15:21 - 15:31
wafer2141-175156-1903533232026-10-23 03:07 - 03:16
wafer1176-207194-2253231132026-10-23 01:16 - 01:25

The reel

✓ Good 194 ? Placed, unverified 13 ! Placed, suspect 0 ↻ Flipped 0 first off the reel → wafer6 TQVE #207 placed (pocket ~222), #1 off (pocket ~4) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S2_0/C8R4 Good 1 TQVE #206 placed (pocket ~221), #2 off (pocket ~5) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S2_-1/C8R4 Good 2 TQVE #205 placed (pocket ~220), #3 off (pocket ~6) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S2_-2/C8R4 Good 3 TQVE #204 placed (pocket ~219), #4 off (pocket ~7) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S1_1/C8R4 Good 4 TQVE #203 placed (pocket ~218), #5 off (pocket ~8) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S1_0/C8R4 Good 5 TQVE #202 placed (pocket ~217), #6 off (pocket ~9) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S1_-1/C8R4 Good 6 TQVE #201 placed (pocket ~216), #7 off (pocket ~10) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S1_-2/C8R4 Good 7 TQVE #200 placed (pocket ~215), #8 off (pocket ~11) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S1_-3/C8R4 Good 8 TQVE #199 placed (pocket ~214), #9 off (pocket ~12) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S1_-4/C8R4 Good 9 TQVE #198 placed (pocket ~213), #10 off (pocket ~13) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S0_2/C8R4 Good 10 TQVE #197 placed (pocket ~212), #11 off (pocket ~14) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S0_1/C8R4 Good 11 TQVE #196 placed (pocket ~211), #12 off (pocket ~15) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S0_0/C8R4 Good 12 TQVE #195 placed (pocket ~210), #13 off (pocket ~16) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S0_-1/C8R4 Good 13 TQVE #194 placed (pocket ~209), #14 off (pocket ~17) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S0_-2/C8R4 Good 14 TQVE #193 placed (pocket ~208), #15 off (pocket ~18) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S0_-3/C8R4 Good 15 TQVE #192 placed (pocket ~207), #16 off (pocket ~19) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S0_-4/C8R4 Placed, unverified 16 TQVE #191 placed (pocket ~206), #17 off (pocket ~20) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-1_2/C8R4 Good 17 TQVE #190 placed (pocket ~205), #18 off (pocket ~21) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-1_1/C8R4 Good 18 TQVE #189 placed (pocket ~204), #19 off (pocket ~22) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-1_0/C8R4 Good 19 TQVE #188 placed (pocket ~203), #20 off (pocket ~23) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-1_-1/C8R4 Good 20 TQVE #187 placed (pocket ~202), #21 off (pocket ~24) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-1_-2/C8R4 Good 21 TQVE #186 placed (pocket ~201), #22 off (pocket ~25) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-1_-3/C8R4 Placed, unverified 22 TQVE #185 placed (pocket ~200), #23 off (pocket ~26) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-1_-4/C8R4 Good 23 TQVE #184 placed (pocket ~199), #24 off (pocket ~27) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-2_2/C8R4 Good 24 TQVE #183 placed (pocket ~198), #25 off (pocket ~28) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-2_1/C8R4 Good 25 TQVE #182 placed (pocket ~197), #26 off (pocket ~29) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-2_0/C8R4 Good 26 TQVE #181 placed (pocket ~196), #27 off (pocket ~30) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-2_-1/C8R4 Good 27 TQVE #180 placed (pocket ~195), #28 off (pocket ~31) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-2_-2/C8R4 Good 28 TQVE #179 placed (pocket ~194), #29 off (pocket ~32) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-2_-3/C8R4 Placed, unverified 29 TQVE #178 placed (pocket ~193), #30 off (pocket ~33) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-2_-4/C8R4 Good 30 TQVE #177 placed (pocket ~192), #31 off (pocket ~34) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-3_1/C8R4 Good 31 TQVE #176 placed (pocket ~191), #32 off (pocket ~35) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-3_0/C8R4 Good 32 TQVE #175 placed (pocket ~190), #33 off (pocket ~36) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-3_-1/C8R4 Good 33 TQVE #174 placed (pocket ~189), #34 off (pocket ~37) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-3_-2/C8R4 Good 34 TQVE #173 placed (pocket ~188), #35 off (pocket ~38) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer6 S-3_-3/C8R4 Good 35 35 dies wafer5 TQVE #172 placed (pocket ~184), #36 off (pocket ~42) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S2_0/C8R4 Good 36 TQVE #171 placed (pocket ~183), #37 off (pocket ~43) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S2_-1/C8R4 Good 37 TQVE #170 placed (pocket ~182), #38 off (pocket ~44) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S2_-2/C8R4 Good 38 TQVE #169 placed (pocket ~181), #39 off (pocket ~45) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S1_1/C8R4 Good 39 TQVE #168 placed (pocket ~180), #40 off (pocket ~46) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S1_0/C8R4 Placed, unverified 40 TQVE #167 placed (pocket ~179), #41 off (pocket ~47) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S1_-1/C8R4 Good 41 TQVE #166 placed (pocket ~178), #42 off (pocket ~48) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S1_-2/C8R4 Good 42 TQVE #165 placed (pocket ~177), #43 off (pocket ~49) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S1_-3/C8R4 Placed, unverified 43 TQVE #164 placed (pocket ~176), #44 off (pocket ~50) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S1_-4/C8R4 Placed, unverified 44 TQVE #163 placed (pocket ~175), #45 off (pocket ~51) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S0_2/C8R4 Good 45 TQVE #162 placed (pocket ~174), #46 off (pocket ~52) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S0_1/C8R4 Good 46 TQVE #161 placed (pocket ~173), #47 off (pocket ~53) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S0_0/C8R4 Good 47 TQVE #160 placed (pocket ~172), #48 off (pocket ~54) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S0_-1/C8R4 Good 48 TQVE #159 placed (pocket ~171), #49 off (pocket ~55) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S0_-2/C8R4 Good 49 TQVE #158 placed (pocket ~170), #50 off (pocket ~56) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S0_-3/C8R4 Good 50 TQVE #157 placed (pocket ~169), #51 off (pocket ~57) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S0_-4/C8R4 Good 51 TQVE #156 placed (pocket ~168), #52 off (pocket ~58) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-1_2/C8R4 Good 52 TQVE #155 placed (pocket ~167), #53 off (pocket ~59) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-1_1/C8R4 Good 53 TQVE #154 placed (pocket ~166), #54 off (pocket ~60) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-1_0/C8R4 Good 54 TQVE #153 placed (pocket ~165), #55 off (pocket ~61) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-1_-1/C8R4 Good 55 TQVE #152 placed (pocket ~164), #56 off (pocket ~62) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-1_-2/C8R4 Good 56 TQVE #151 placed (pocket ~163), #57 off (pocket ~63) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-1_-3/C8R4 Good 57 TQVE #150 placed (pocket ~162), #58 off (pocket ~64) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-1_-4/C8R4 Good 58 TQVE #149 placed (pocket ~161), #59 off (pocket ~65) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-2_2/C8R4 Good 59 TQVE #148 placed (pocket ~160), #60 off (pocket ~66) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-2_1/C8R4 Good 60 TQVE #147 placed (pocket ~159), #61 off (pocket ~67) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-2_0/C8R4 Good 61 TQVE #146 placed (pocket ~158), #62 off (pocket ~68) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-2_-1/C8R4 Good 62 TQVE #145 placed (pocket ~157), #63 off (pocket ~69) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-2_-2/C8R4 Good 63 TQVE #144 placed (pocket ~156), #64 off (pocket ~70) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-2_-3/C8R4 Good 64 TQVE #143 placed (pocket ~155), #65 off (pocket ~71) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-2_-4/C8R4 Good 65 TQVE #142 placed (pocket ~154), #66 off (pocket ~72) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-3_1/C8R4 Good 66 TQVE #141 placed (pocket ~153), #67 off (pocket ~73) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-3_0/C8R4 Good 67 TQVE #140 placed (pocket ~152), #68 off (pocket ~74) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-3_-1/C8R4 Good 68 TQVE #139 placed (pocket ~151), #69 off (pocket ~75) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-3_-2/C8R4 Good 69 TQVE #138 placed (pocket ~150), #70 off (pocket ~76) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer5 S-3_-3/C8R4 Good 70 35 dies wafer4 TQVE #137 placed (pocket ~146), #71 off (pocket ~80) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S2_0/C8R4 Good 71 TQVE #136 placed (pocket ~145), #72 off (pocket ~81) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S2_-1/C8R4 Good 72 TQVE #135 placed (pocket ~144), #73 off (pocket ~82) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S2_-2/C8R4 Good 73 TQVE #134 placed (pocket ~143), #74 off (pocket ~83) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S1_1/C8R4 Good 74 TQVE #133 placed (pocket ~142), #75 off (pocket ~84) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S1_0/C8R4 Good 75 TQVE #132 placed (pocket ~141), #76 off (pocket ~85) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S1_-1/C8R4 Good 76 TQVE #131 placed (pocket ~140), #77 off (pocket ~86) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S1_-2/C8R4 Good 77 TQVE #130 placed (pocket ~139), #78 off (pocket ~87) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S1_-3/C8R4 Good 78 TQVE #129 placed (pocket ~138), #79 off (pocket ~88) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S1_-4/C8R4 Good 79 TQVE #128 placed (pocket ~137), #80 off (pocket ~89) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S0_2/C8R4 Good 80 TQVE #127 placed (pocket ~136), #81 off (pocket ~90) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S0_1/C8R4 Good 81 TQVE #126 placed (pocket ~135), #82 off (pocket ~91) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S0_0/C8R4 Good 82 TQVE #125 placed (pocket ~134), #83 off (pocket ~92) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S0_-1/C8R4 Good 83 TQVE #124 placed (pocket ~133), #84 off (pocket ~93) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S0_-2/C8R4 Good 84 TQVE #123 placed (pocket ~132), #85 off (pocket ~94) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S0_-3/C8R4 Good 85 TQVE #122 placed (pocket ~131), #86 off (pocket ~95) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S0_-4/C8R4 Good 86 TQVE #121 placed (pocket ~130), #87 off (pocket ~96) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-1_2/C8R4 Placed, unverified 87 TQVE #120 placed (pocket ~129), #88 off (pocket ~97) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-1_1/C8R4 Good 88 TQVE #119 placed (pocket ~128), #89 off (pocket ~98) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-1_0/C8R4 Good 89 TQVE #118 placed (pocket ~127), #90 off (pocket ~99) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-1_-1/C8R4 Good 90 TQVE #117 placed (pocket ~126), #91 off (pocket ~100) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-1_-2/C8R4 Good 91 TQVE #116 placed (pocket ~125), #92 off (pocket ~101) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-1_-3/C8R4 Good 92 TQVE #115 placed (pocket ~124), #93 off (pocket ~102) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-1_-4/C8R4 Good 93 TQVE #114 placed (pocket ~123), #94 off (pocket ~103) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-2_2/C8R4 Good 94 TQVE #113 placed (pocket ~122), #95 off (pocket ~104) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-2_1/C8R4 Good 95 TQVE #112 placed (pocket ~121), #96 off (pocket ~105) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-2_0/C8R4 Good 96 TQVE #111 placed (pocket ~120), #97 off (pocket ~106) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-2_-1/C8R4 Good 97 TQVE #110 placed (pocket ~119), #98 off (pocket ~107) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-2_-2/C8R4 Good 98 TQVE #109 placed (pocket ~118), #99 off (pocket ~108) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-2_-3/C8R4 Good 99 TQVE #108 placed (pocket ~117), #100 off (pocket ~109) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-2_-4/C8R4 Good 100 TQVE #107 placed (pocket ~116), #101 off (pocket ~110) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-3_1/C8R4 Good 101 TQVE #106 placed (pocket ~115), #102 off (pocket ~111) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-3_0/C8R4 Good 102 TQVE #105 placed (pocket ~114), #103 off (pocket ~112) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-3_-1/C8R4 Good 103 TQVE #104 placed (pocket ~113), #104 off (pocket ~113) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-3_-2/C8R4 Good 104 TQVE #103 placed (pocket ~112), #105 off (pocket ~114) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer4 S-3_-3/C8R4 Good 105 35 dies wafer3 TQVE #102 placed (pocket ~108), #106 off (pocket ~118) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S2_0/C8R4 Good 106 TQVE #101 placed (pocket ~107), #107 off (pocket ~119) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S2_-1/C8R4 Good 107 TQVE #100 placed (pocket ~106), #108 off (pocket ~120) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S2_-2/C8R4 Good 108 TQVE #99 placed (pocket ~105), #109 off (pocket ~121) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S1_1/C8R4 Good 109 TQVE #98 placed (pocket ~104), #110 off (pocket ~122) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S1_0/C8R4 Good 110 TQVE #97 placed (pocket ~103), #111 off (pocket ~123) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S1_-1/C8R4 Good 111 TQVE #96 placed (pocket ~102), #112 off (pocket ~124) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S1_-2/C8R4 Good 112 TQVE #95 placed (pocket ~101), #113 off (pocket ~125) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S1_-3/C8R4 Good 113 TQVE #94 placed (pocket ~100), #114 off (pocket ~126) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S1_-4/C8R4 Good 114 TQVE #93 placed (pocket ~99), #115 off (pocket ~127) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S0_2/C8R4 Good 115 TQVE #92 placed (pocket ~98), #116 off (pocket ~128) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S0_1/C8R4 Good 116 TQVE #91 placed (pocket ~97), #117 off (pocket ~129) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S0_0/C8R4 Placed, unverified 117 TQVE #90 placed (pocket ~96), #118 off (pocket ~130) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S0_-1/C8R4 Good 118 TQVE #89 placed (pocket ~95), #119 off (pocket ~131) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S0_-2/C8R4 Placed, unverified 119 TQVE #88 placed (pocket ~94), #120 off (pocket ~132) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S0_-3/C8R4 Good 120 TQVE #87 placed (pocket ~93), #121 off (pocket ~133) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S0_-4/C8R4 Good 121 TQVE #86 placed (pocket ~92), #122 off (pocket ~134) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-1_2/C8R4 Good 122 TQVE #85 placed (pocket ~91), #123 off (pocket ~135) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-1_1/C8R4 Good 123 TQVE #84 placed (pocket ~90), #124 off (pocket ~136) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-1_0/C8R4 Good 124 TQVE #83 placed (pocket ~89), #125 off (pocket ~137) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-1_-1/C8R4 Placed, unverified 125 TQVE #82 placed (pocket ~88), #126 off (pocket ~138) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-1_-2/C8R4 Good 126 TQVE #81 placed (pocket ~87), #127 off (pocket ~139) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-1_-3/C8R4 Good 127 TQVE #80 placed (pocket ~86), #128 off (pocket ~140) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-1_-4/C8R4 Good 128 TQVE #79 placed (pocket ~85), #129 off (pocket ~141) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-2_2/C8R4 Good 129 TQVE #78 placed (pocket ~84), #130 off (pocket ~142) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-2_1/C8R4 Good 130 TQVE #77 placed (pocket ~83), #131 off (pocket ~143) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-2_0/C8R4 Good 131 TQVE #76 placed (pocket ~82), #132 off (pocket ~144) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-2_-1/C8R4 Good 132 TQVE #75 placed (pocket ~81), #133 off (pocket ~145) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-2_-2/C8R4 Good 133 TQVE #74 placed (pocket ~80), #134 off (pocket ~146) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-2_-3/C8R4 Good 134 TQVE #73 placed (pocket ~79), #135 off (pocket ~147) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-2_-4/C8R4 Good 135 TQVE #72 placed (pocket ~78), #136 off (pocket ~148) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-3_1/C8R4 Good 136 TQVE #71 placed (pocket ~77), #137 off (pocket ~149) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-3_0/C8R4 Good 137 TQVE #70 placed (pocket ~76), #138 off (pocket ~150) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-3_-1/C8R4 Good 138 TQVE #69 placed (pocket ~75), #139 off (pocket ~151) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-3_-2/C8R4 Good 139 TQVE #68 placed (pocket ~74), #140 off (pocket ~152) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer3 S-3_-3/C8R4 Good 140 35 dies wafer2 TQVE #67 placed (pocket ~70), #141 off (pocket ~156) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S2_0/C8R4 Good 141 TQVE #66 placed (pocket ~69), #142 off (pocket ~157) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S2_-1/C8R4 Good 142 TQVE #65 placed (pocket ~68), #143 off (pocket ~158) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S2_-2/C8R4 Good 143 TQVE #64 placed (pocket ~67), #144 off (pocket ~159) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S1_1/C8R4 Good 144 TQVE #63 placed (pocket ~66), #145 off (pocket ~160) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S1_0/C8R4 Good 145 TQVE #62 placed (pocket ~65), #146 off (pocket ~161) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S1_-1/C8R4 Good 146 TQVE #61 placed (pocket ~64), #147 off (pocket ~162) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S1_-2/C8R4 Good 147 TQVE #60 placed (pocket ~63), #148 off (pocket ~163) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S1_-3/C8R4 Good 148 TQVE #59 placed (pocket ~62), #149 off (pocket ~164) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S1_-4/C8R4 Placed, unverified 149 TQVE #58 placed (pocket ~61), #150 off (pocket ~165) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S0_2/C8R4 Good 150 TQVE #57 placed (pocket ~60), #151 off (pocket ~166) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S0_1/C8R4 Good 151 TQVE #56 placed (pocket ~59), #152 off (pocket ~167) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S0_0/C8R4 Good 152 TQVE #55 placed (pocket ~58), #153 off (pocket ~168) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S0_-1/C8R4 Good 153 TQVE #54 placed (pocket ~57), #154 off (pocket ~169) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S0_-2/C8R4 Good 154 TQVE #53 placed (pocket ~56), #155 off (pocket ~170) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S0_-3/C8R4 Good 155 TQVE #52 placed (pocket ~55), #156 off (pocket ~171) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S0_-4/C8R4 Good 156 TQVE #51 placed (pocket ~54), #157 off (pocket ~172) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-1_2/C8R4 Good 157 TQVE #50 placed (pocket ~53), #158 off (pocket ~173) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-1_1/C8R4 Good 158 TQVE #49 placed (pocket ~52), #159 off (pocket ~174) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-1_0/C8R4 Good 159 TQVE #48 placed (pocket ~51), #160 off (pocket ~175) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-1_-1/C8R4 Good 160 TQVE #47 placed (pocket ~50), #161 off (pocket ~176) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-1_-2/C8R4 Good 161 TQVE #46 placed (pocket ~49), #162 off (pocket ~177) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-1_-3/C8R4 Good 162 TQVE #45 placed (pocket ~48), #163 off (pocket ~178) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-1_-4/C8R4 Good 163 TQVE #44 placed (pocket ~47), #164 off (pocket ~179) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-2_2/C8R4 Good 164 TQVE #43 placed (pocket ~46), #165 off (pocket ~180) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-2_1/C8R4 Good 165 TQVE #42 placed (pocket ~45), #166 off (pocket ~181) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-2_0/C8R4 Good 166 TQVE #41 placed (pocket ~44), #167 off (pocket ~182) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-2_-1/C8R4 Good 167 TQVE #40 placed (pocket ~43), #168 off (pocket ~183) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-2_-2/C8R4 Good 168 TQVE #39 placed (pocket ~42), #169 off (pocket ~184) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-2_-3/C8R4 Good 169 TQVE #38 placed (pocket ~41), #170 off (pocket ~185) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-2_-4/C8R4 Good 170 TQVE #37 placed (pocket ~40), #171 off (pocket ~186) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-3_1/C8R4 Placed, unverified 171 TQVE #36 placed (pocket ~39), #172 off (pocket ~187) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-3_0/C8R4 Good 172 TQVE #35 placed (pocket ~38), #173 off (pocket ~188) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-3_-1/C8R4 Good 173 TQVE #34 placed (pocket ~37), #174 off (pocket ~189) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-3_-2/C8R4 Good 174 TQVE #33 placed (pocket ~36), #175 off (pocket ~190) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer2 S-3_-3/C8R4 Good 175 35 dies wafer1 TQVE #32 placed (pocket ~32), #176 off (pocket ~194) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S2_0/C8R4 Good 176 TQVE #31 placed (pocket ~31), #177 off (pocket ~195) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S2_-1/C8R4 Good 177 TQVE #30 placed (pocket ~30), #178 off (pocket ~196) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S2_-2/C8R4 Good 178 TQVE #29 placed (pocket ~29), #179 off (pocket ~197) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S1_1/C8R4 Good 179 TQVE #28 placed (pocket ~28), #180 off (pocket ~198) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S1_0/C8R4 Good 180 TQVE #27 placed (pocket ~27), #181 off (pocket ~199) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S1_-1/C8R4 Good 181 TQVE #26 placed (pocket ~26), #182 off (pocket ~200) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S1_-2/C8R4 Good 182 TQVE #25 placed (pocket ~25), #183 off (pocket ~201) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S1_-3/C8R4 Good 183 TQVE #24 placed (pocket ~24), #184 off (pocket ~202) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S1_-4/C8R4 Placed, unverified 184 TQVE #23 placed (pocket ~23), #185 off (pocket ~203) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S0_2/C8R4 Good 185 TQVE #22 placed (pocket ~22), #186 off (pocket ~204) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S0_1/C8R4 Good 186 TQVE #21 placed (pocket ~21), #187 off (pocket ~205) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S0_0/C8R4 Good 187 TQVE #20 placed (pocket ~20), #188 off (pocket ~206) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S0_-1/C8R4 Good 188 TQVE #19 placed (pocket ~19), #189 off (pocket ~207) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S0_-2/C8R4 Good 189 TQVE #18 placed (pocket ~18), #190 off (pocket ~208) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S0_-3/C8R4 Good 190 TQVE #17 placed (pocket ~17), #191 off (pocket ~209) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S0_-4/C8R4 Good 191 TQVE #16 placed (pocket ~16), #192 off (pocket ~210) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S-1_2/C8R4 Good 192 TQVE #15 placed (pocket ~15), #193 off (pocket ~211) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S-1_1/C8R4 Good 193 TQVE #14 placed (pocket ~14), #194 off (pocket ~212) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S-1_0/C8R4 Good 194 TQVE #13 placed (pocket ~13), #195 off (pocket ~213) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S-1_-1/C8R4 Good 195 TQVE #12 placed (pocket ~12), #196 off (pocket ~214) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S-1_-2/C8R4 Good 196 TQVE #11 placed (pocket ~11), #197 off (pocket ~215) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S-1_-3/C8R4 Good 197 TQVE #10 placed (pocket ~10), #198 off (pocket ~216) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S-1_-4/C8R4 Good 198 TQVE #9 placed (pocket ~9), #199 off (pocket ~217) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S-2_2/C8R4 Good 199 TQVE #8 placed (pocket ~8), #200 off (pocket ~218) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S-2_1/C8R4 Good 200 TQVE #7 placed (pocket ~7), #201 off (pocket ~219) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S-2_0/C8R4 Good 201 TQVE #6 placed (pocket ~6), #202 off (pocket ~220) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S-2_-1/C8R4 Good 202 TQVE #5 placed (pocket ~5), #203 off (pocket ~221) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S-2_-4/C8R4 Good 203 TQVE #4 placed (pocket ~4), #204 off (pocket ~222) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S-3_1/C8R4 Good 204 TQVE #3 placed (pocket ~3), #205 off (pocket ~223) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S-3_0/C8R4 Good 205 TQVE #2 placed (pocket ~2), #206 off (pocket ~224) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S-3_-2/C8R4 Good 206 TQVE #1 placed (pocket ~1), #207 off (pocket ~225) TQVE - TinyQV - RISC-V SoC with experimental pad setup wafer1 S-3_-3/C8R4 Good 207 32 dies

Every pocket

PocketDieWaferReticleNote
1empty
2empty
3empty
41wafer6S2_0/C8R4
52wafer6S2_-1/C8R4
63wafer6S2_-2/C8R4
74wafer6S1_1/C8R4
85wafer6S1_0/C8R4
96wafer6S1_-1/C8R4
107wafer6S1_-2/C8R4
118wafer6S1_-3/C8R4
129wafer6S1_-4/C8R4
1310wafer6S0_2/C8R4
1411wafer6S0_1/C8R4
1512wafer6S0_0/C8R4
1613wafer6S0_-1/C8R4
1714wafer6S0_-2/C8R4
1815wafer6S0_-3/C8R4
1916wafer6S0_-4/C8R4? Unverified
2017wafer6S-1_2/C8R4
2118wafer6S-1_1/C8R4
2219wafer6S-1_0/C8R4
2320wafer6S-1_-1/C8R4
2421wafer6S-1_-2/C8R4
2522wafer6S-1_-3/C8R4? Unverified
2623wafer6S-1_-4/C8R4
2724wafer6S-2_2/C8R4
2825wafer6S-2_1/C8R4
2926wafer6S-2_0/C8R4
3027wafer6S-2_-1/C8R4
3128wafer6S-2_-2/C8R4
3229wafer6S-2_-3/C8R4? Unverified
3330wafer6S-2_-4/C8R4
3431wafer6S-3_1/C8R4
3532wafer6S-3_0/C8R4
3633wafer6S-3_-1/C8R4
3734wafer6S-3_-2/C8R4
3835wafer6S-3_-3/C8R4
39empty
40empty
41empty
4236wafer5S2_0/C8R4
4337wafer5S2_-1/C8R4
4438wafer5S2_-2/C8R4
4539wafer5S1_1/C8R4
4640wafer5S1_0/C8R4? Unverified
4741wafer5S1_-1/C8R4
4842wafer5S1_-2/C8R4
4943wafer5S1_-3/C8R4? Unverified
5044wafer5S1_-4/C8R4? Unverified
5145wafer5S0_2/C8R4
5246wafer5S0_1/C8R4
5347wafer5S0_0/C8R4
5448wafer5S0_-1/C8R4
5549wafer5S0_-2/C8R4
5650wafer5S0_-3/C8R4
5751wafer5S0_-4/C8R4
5852wafer5S-1_2/C8R4
5953wafer5S-1_1/C8R4
6054wafer5S-1_0/C8R4
6155wafer5S-1_-1/C8R4
6256wafer5S-1_-2/C8R4
6357wafer5S-1_-3/C8R4
6458wafer5S-1_-4/C8R4
6559wafer5S-2_2/C8R4
6660wafer5S-2_1/C8R4
6761wafer5S-2_0/C8R4
6862wafer5S-2_-1/C8R4
6963wafer5S-2_-2/C8R4
7064wafer5S-2_-3/C8R4
7165wafer5S-2_-4/C8R4
7266wafer5S-3_1/C8R4
7367wafer5S-3_0/C8R4
7468wafer5S-3_-1/C8R4
7569wafer5S-3_-2/C8R4
7670wafer5S-3_-3/C8R4
77empty
78empty
79empty
8071wafer4S2_0/C8R4
8172wafer4S2_-1/C8R4
8273wafer4S2_-2/C8R4
8374wafer4S1_1/C8R4
8475wafer4S1_0/C8R4
8576wafer4S1_-1/C8R4
8677wafer4S1_-2/C8R4
8778wafer4S1_-3/C8R4
8879wafer4S1_-4/C8R4
8980wafer4S0_2/C8R4
9081wafer4S0_1/C8R4
9182wafer4S0_0/C8R4
9283wafer4S0_-1/C8R4
9384wafer4S0_-2/C8R4
9485wafer4S0_-3/C8R4
9586wafer4S0_-4/C8R4
9687wafer4S-1_2/C8R4? Unverified
9788wafer4S-1_1/C8R4
9889wafer4S-1_0/C8R4
9990wafer4S-1_-1/C8R4
10091wafer4S-1_-2/C8R4
10192wafer4S-1_-3/C8R4
10293wafer4S-1_-4/C8R4
10394wafer4S-2_2/C8R4
10495wafer4S-2_1/C8R4
10596wafer4S-2_0/C8R4
10697wafer4S-2_-1/C8R4
10798wafer4S-2_-2/C8R4
10899wafer4S-2_-3/C8R4
109100wafer4S-2_-4/C8R4
110101wafer4S-3_1/C8R4
111102wafer4S-3_0/C8R4
112103wafer4S-3_-1/C8R4
113104wafer4S-3_-2/C8R4
114105wafer4S-3_-3/C8R4
115empty
116empty
117empty
118106wafer3S2_0/C8R4
119107wafer3S2_-1/C8R4
120108wafer3S2_-2/C8R4
121109wafer3S1_1/C8R4
122110wafer3S1_0/C8R4
123111wafer3S1_-1/C8R4
124112wafer3S1_-2/C8R4
125113wafer3S1_-3/C8R4
126114wafer3S1_-4/C8R4
127115wafer3S0_2/C8R4
128116wafer3S0_1/C8R4
129117wafer3S0_0/C8R4? Unverified
130118wafer3S0_-1/C8R4
131119wafer3S0_-2/C8R4? Unverified
132120wafer3S0_-3/C8R4
133121wafer3S0_-4/C8R4
134122wafer3S-1_2/C8R4
135123wafer3S-1_1/C8R4
136124wafer3S-1_0/C8R4
137125wafer3S-1_-1/C8R4? Unverified
138126wafer3S-1_-2/C8R4
139127wafer3S-1_-3/C8R4
140128wafer3S-1_-4/C8R4
141129wafer3S-2_2/C8R4
142130wafer3S-2_1/C8R4
143131wafer3S-2_0/C8R4
144132wafer3S-2_-1/C8R4
145133wafer3S-2_-2/C8R4
146134wafer3S-2_-3/C8R4
147135wafer3S-2_-4/C8R4
148136wafer3S-3_1/C8R4
149137wafer3S-3_0/C8R4
150138wafer3S-3_-1/C8R4
151139wafer3S-3_-2/C8R4
152140wafer3S-3_-3/C8R4
153empty
154empty
155empty
156141wafer2S2_0/C8R4
157142wafer2S2_-1/C8R4
158143wafer2S2_-2/C8R4
159144wafer2S1_1/C8R4
160145wafer2S1_0/C8R4
161146wafer2S1_-1/C8R4
162147wafer2S1_-2/C8R4
163148wafer2S1_-3/C8R4
164149wafer2S1_-4/C8R4? Unverified
165150wafer2S0_2/C8R4
166151wafer2S0_1/C8R4
167152wafer2S0_0/C8R4
168153wafer2S0_-1/C8R4
169154wafer2S0_-2/C8R4
170155wafer2S0_-3/C8R4
171156wafer2S0_-4/C8R4
172157wafer2S-1_2/C8R4
173158wafer2S-1_1/C8R4
174159wafer2S-1_0/C8R4
175160wafer2S-1_-1/C8R4
176161wafer2S-1_-2/C8R4
177162wafer2S-1_-3/C8R4
178163wafer2S-1_-4/C8R4
179164wafer2S-2_2/C8R4
180165wafer2S-2_1/C8R4
181166wafer2S-2_0/C8R4
182167wafer2S-2_-1/C8R4
183168wafer2S-2_-2/C8R4
184169wafer2S-2_-3/C8R4
185170wafer2S-2_-4/C8R4
186171wafer2S-3_1/C8R4? Unverified
187172wafer2S-3_0/C8R4
188173wafer2S-3_-1/C8R4
189174wafer2S-3_-2/C8R4
190175wafer2S-3_-3/C8R4
191empty
192empty
193empty
194176wafer1S2_0/C8R4
195177wafer1S2_-1/C8R4
196178wafer1S2_-2/C8R4
197179wafer1S1_1/C8R4
198180wafer1S1_0/C8R4
199181wafer1S1_-1/C8R4
200182wafer1S1_-2/C8R4
201183wafer1S1_-3/C8R4
202184wafer1S1_-4/C8R4? Unverified
203185wafer1S0_2/C8R4
204186wafer1S0_1/C8R4
205187wafer1S0_0/C8R4
206188wafer1S0_-1/C8R4
207189wafer1S0_-2/C8R4
208190wafer1S0_-3/C8R4
209191wafer1S0_-4/C8R4
210192wafer1S-1_2/C8R4
211193wafer1S-1_1/C8R4
212194wafer1S-1_0/C8R4
213195wafer1S-1_-1/C8R4
214196wafer1S-1_-2/C8R4
215197wafer1S-1_-3/C8R4
216198wafer1S-1_-4/C8R4
217199wafer1S-2_2/C8R4
218200wafer1S-2_1/C8R4
219201wafer1S-2_0/C8R4
220202wafer1S-2_-1/C8R4
221203wafer1S-2_-4/C8R4
222204wafer1S-3_1/C8R4
223205wafer1S-3_0/C8R4
224206wafer1S-3_-2/C8R4
225207wafer1S-3_-3/C8R4