Reel DCO0

Standard Cell DCO+TDC · die sort run2 · made 2026-11-03

DCO0 in its pocket
DCO0 in its pocket
ReelDCO0
ProjectDCO0 - Standard Cell DCO+TDC
Die size1x0p5 (width x height, of a 4.0 x 5.18 mm slot)
Batchrun2
Die orderAs it comes off: #1 is the first die off, the last one placed
Dies on the reel202, in 220 pockets (est.)
Empty pockets18, logged by the machine between wafers
Flipped, die #none
Suspect, die #none
Unverified, die #29, 81, 91, 99, 141, 153
Lost, not on the reel6 of this project's dies (dropped, missed or taken back out)

Wafer by wafer

WaferDie #Pockets (est.)Dies GoodUnverifiedSuspectFlipped Empty beforePlaced
wafer61-314-343130132026-10-24 15:30 - 15:54
wafer532-6638-72353532026-10-24 14:07 - 14:16
wafer467-10176-1103532332026-10-24 03:23 - 03:33
wafer3102-136114-148353532026-10-24 01:49 - 02:00
wafer2137-170152-1853432232026-10-24 00:21 - 00:33
wafer1171-201189-219313132026-10-23 22:54 - 23:03
wafer6202-202220-2201102026-10-23 22:51 - 22:51

The reel

✓ Good 196 ? Placed, unverified 6 ! Placed, suspect 0 ↻ Flipped 0 first off the reel → wafer6 DCO0 #202 placed (pocket ~217), #1 off (pocket ~4) DCO0 - Standard Cell DCO+TDC wafer6 S2_1/C0R3 Good 1 DCO0 #201 placed (pocket ~216), #2 off (pocket ~5) DCO0 - Standard Cell DCO+TDC wafer6 S2_0/C0R3 Good 2 DCO0 #200 placed (pocket ~215), #3 off (pocket ~6) DCO0 - Standard Cell DCO+TDC wafer6 S2_-1/C0R3 Good 3 DCO0 #199 placed (pocket ~214), #4 off (pocket ~7) DCO0 - Standard Cell DCO+TDC wafer6 S2_-2/C0R3 Good 4 DCO0 #198 placed (pocket ~213), #5 off (pocket ~8) DCO0 - Standard Cell DCO+TDC wafer6 S2_-3/C0R3 Good 5 DCO0 #197 placed (pocket ~212), #6 off (pocket ~9) DCO0 - Standard Cell DCO+TDC wafer6 S1_2/C0R3 Good 6 DCO0 #196 placed (pocket ~211), #7 off (pocket ~10) DCO0 - Standard Cell DCO+TDC wafer6 S1_1/C0R3 Good 7 DCO0 #195 placed (pocket ~210), #8 off (pocket ~11) DCO0 - Standard Cell DCO+TDC wafer6 S1_0/C0R3 Good 8 DCO0 #194 placed (pocket ~209), #9 off (pocket ~12) DCO0 - Standard Cell DCO+TDC wafer6 S1_-1/C0R3 Good 9 DCO0 #193 placed (pocket ~208), #10 off (pocket ~13) DCO0 - Standard Cell DCO+TDC wafer6 S1_-2/C0R3 Good 10 DCO0 #192 placed (pocket ~207), #11 off (pocket ~14) DCO0 - Standard Cell DCO+TDC wafer6 S1_-3/C0R3 Good 11 DCO0 #191 placed (pocket ~206), #12 off (pocket ~15) DCO0 - Standard Cell DCO+TDC wafer6 S1_-4/C0R3 Good 12 DCO0 #190 placed (pocket ~205), #13 off (pocket ~16) DCO0 - Standard Cell DCO+TDC wafer6 S0_2/C0R3 Good 13 DCO0 #189 placed (pocket ~204), #14 off (pocket ~17) DCO0 - Standard Cell DCO+TDC wafer6 S0_1/C0R3 Good 14 DCO0 #188 placed (pocket ~203), #15 off (pocket ~18) DCO0 - Standard Cell DCO+TDC wafer6 S0_0/C0R3 Good 15 DCO0 #187 placed (pocket ~202), #16 off (pocket ~19) DCO0 - Standard Cell DCO+TDC wafer6 S0_-1/C0R3 Good 16 DCO0 #186 placed (pocket ~201), #17 off (pocket ~20) DCO0 - Standard Cell DCO+TDC wafer6 S0_-2/C0R3 Good 17 DCO0 #185 placed (pocket ~200), #18 off (pocket ~21) DCO0 - Standard Cell DCO+TDC wafer6 S0_-3/C0R3 Good 18 DCO0 #184 placed (pocket ~199), #19 off (pocket ~22) DCO0 - Standard Cell DCO+TDC wafer6 S0_-4/C0R3 Good 19 DCO0 #183 placed (pocket ~198), #20 off (pocket ~23) DCO0 - Standard Cell DCO+TDC wafer6 S-1_2/C0R3 Good 20 DCO0 #182 placed (pocket ~197), #21 off (pocket ~24) DCO0 - Standard Cell DCO+TDC wafer6 S-1_1/C0R3 Good 21 DCO0 #181 placed (pocket ~196), #22 off (pocket ~25) DCO0 - Standard Cell DCO+TDC wafer6 S-1_0/C0R3 Good 22 DCO0 #180 placed (pocket ~195), #23 off (pocket ~26) DCO0 - Standard Cell DCO+TDC wafer6 S-1_-1/C0R3 Good 23 DCO0 #179 placed (pocket ~194), #24 off (pocket ~27) DCO0 - Standard Cell DCO+TDC wafer6 S-1_-2/C0R3 Good 24 DCO0 #178 placed (pocket ~193), #25 off (pocket ~28) DCO0 - Standard Cell DCO+TDC wafer6 S-1_-3/C0R3 Good 25 DCO0 #177 placed (pocket ~192), #26 off (pocket ~29) DCO0 - Standard Cell DCO+TDC wafer6 S-1_-4/C0R3 Good 26 DCO0 #176 placed (pocket ~191), #27 off (pocket ~30) DCO0 - Standard Cell DCO+TDC wafer6 S-2_1/C0R3 Good 27 DCO0 #175 placed (pocket ~190), #28 off (pocket ~31) DCO0 - Standard Cell DCO+TDC wafer6 S-2_0/C0R3 Good 28 DCO0 #174 placed (pocket ~189), #29 off (pocket ~32) DCO0 - Standard Cell DCO+TDC wafer6 S-2_-1/C0R3 Placed, unverified 29 DCO0 #173 placed (pocket ~188), #30 off (pocket ~33) DCO0 - Standard Cell DCO+TDC wafer6 S-2_-2/C0R3 Good 30 DCO0 #172 placed (pocket ~187), #31 off (pocket ~34) DCO0 - Standard Cell DCO+TDC wafer6 S-3_0/C0R3 Good 31 DCO0 #1 placed (pocket ~1), #202 off (pocket ~220) DCO0 - Standard Cell DCO+TDC wafer6 S-3_-2/C0R3 Good 202 32 dies wafer5 DCO0 #171 placed (pocket ~183), #32 off (pocket ~38) DCO0 - Standard Cell DCO+TDC wafer5 S2_1/C0R3 Good 32 DCO0 #170 placed (pocket ~182), #33 off (pocket ~39) DCO0 - Standard Cell DCO+TDC wafer5 S2_0/C0R3 Good 33 DCO0 #169 placed (pocket ~181), #34 off (pocket ~40) DCO0 - Standard Cell DCO+TDC wafer5 S2_-1/C0R3 Good 34 DCO0 #168 placed (pocket ~180), #35 off (pocket ~41) DCO0 - Standard Cell DCO+TDC wafer5 S2_-2/C0R3 Good 35 DCO0 #167 placed (pocket ~179), #36 off (pocket ~42) DCO0 - Standard Cell DCO+TDC wafer5 S2_-3/C0R3 Good 36 DCO0 #166 placed (pocket ~178), #37 off (pocket ~43) DCO0 - Standard Cell DCO+TDC wafer5 S1_2/C0R3 Good 37 DCO0 #165 placed (pocket ~177), #38 off (pocket ~44) DCO0 - Standard Cell DCO+TDC wafer5 S1_1/C0R3 Good 38 DCO0 #164 placed (pocket ~176), #39 off (pocket ~45) DCO0 - Standard Cell DCO+TDC wafer5 S1_0/C0R3 Good 39 DCO0 #163 placed (pocket ~175), #40 off (pocket ~46) DCO0 - Standard Cell DCO+TDC wafer5 S1_-1/C0R3 Good 40 DCO0 #162 placed (pocket ~174), #41 off (pocket ~47) DCO0 - Standard Cell DCO+TDC wafer5 S1_-2/C0R3 Good 41 DCO0 #161 placed (pocket ~173), #42 off (pocket ~48) DCO0 - Standard Cell DCO+TDC wafer5 S1_-3/C0R3 Good 42 DCO0 #160 placed (pocket ~172), #43 off (pocket ~49) DCO0 - Standard Cell DCO+TDC wafer5 S1_-4/C0R3 Good 43 DCO0 #159 placed (pocket ~171), #44 off (pocket ~50) DCO0 - Standard Cell DCO+TDC wafer5 S0_2/C0R3 Good 44 DCO0 #158 placed (pocket ~170), #45 off (pocket ~51) DCO0 - Standard Cell DCO+TDC wafer5 S0_1/C0R3 Good 45 DCO0 #157 placed (pocket ~169), #46 off (pocket ~52) DCO0 - Standard Cell DCO+TDC wafer5 S0_0/C0R3 Good 46 DCO0 #156 placed (pocket ~168), #47 off (pocket ~53) DCO0 - Standard Cell DCO+TDC wafer5 S0_-1/C0R3 Good 47 DCO0 #155 placed (pocket ~167), #48 off (pocket ~54) DCO0 - Standard Cell DCO+TDC wafer5 S0_-2/C0R3 Good 48 DCO0 #154 placed (pocket ~166), #49 off (pocket ~55) DCO0 - Standard Cell DCO+TDC wafer5 S0_-3/C0R3 Good 49 DCO0 #153 placed (pocket ~165), #50 off (pocket ~56) DCO0 - Standard Cell DCO+TDC wafer5 S0_-4/C0R3 Good 50 DCO0 #152 placed (pocket ~164), #51 off (pocket ~57) DCO0 - Standard Cell DCO+TDC wafer5 S-1_2/C0R3 Good 51 DCO0 #151 placed (pocket ~163), #52 off (pocket ~58) DCO0 - Standard Cell DCO+TDC wafer5 S-1_1/C0R3 Good 52 DCO0 #150 placed (pocket ~162), #53 off (pocket ~59) DCO0 - Standard Cell DCO+TDC wafer5 S-1_0/C0R3 Good 53 DCO0 #149 placed (pocket ~161), #54 off (pocket ~60) DCO0 - Standard Cell DCO+TDC wafer5 S-1_-1/C0R3 Good 54 DCO0 #148 placed (pocket ~160), #55 off (pocket ~61) DCO0 - Standard Cell DCO+TDC wafer5 S-1_-2/C0R3 Good 55 DCO0 #147 placed (pocket ~159), #56 off (pocket ~62) DCO0 - Standard Cell DCO+TDC wafer5 S-1_-3/C0R3 Good 56 DCO0 #146 placed (pocket ~158), #57 off (pocket ~63) DCO0 - Standard Cell DCO+TDC wafer5 S-1_-4/C0R3 Good 57 DCO0 #145 placed (pocket ~157), #58 off (pocket ~64) DCO0 - Standard Cell DCO+TDC wafer5 S-2_1/C0R3 Good 58 DCO0 #144 placed (pocket ~156), #59 off (pocket ~65) DCO0 - Standard Cell DCO+TDC wafer5 S-2_0/C0R3 Good 59 DCO0 #143 placed (pocket ~155), #60 off (pocket ~66) DCO0 - Standard Cell DCO+TDC wafer5 S-2_-1/C0R3 Good 60 DCO0 #142 placed (pocket ~154), #61 off (pocket ~67) DCO0 - Standard Cell DCO+TDC wafer5 S-2_-2/C0R3 Good 61 DCO0 #141 placed (pocket ~153), #62 off (pocket ~68) DCO0 - Standard Cell DCO+TDC wafer5 S-2_-3/C0R3 Good 62 DCO0 #140 placed (pocket ~152), #63 off (pocket ~69) DCO0 - Standard Cell DCO+TDC wafer5 S-2_-4/C0R3 Good 63 DCO0 #139 placed (pocket ~151), #64 off (pocket ~70) DCO0 - Standard Cell DCO+TDC wafer5 S-3_0/C0R3 Good 64 DCO0 #138 placed (pocket ~150), #65 off (pocket ~71) DCO0 - Standard Cell DCO+TDC wafer5 S-3_-1/C0R3 Good 65 DCO0 #137 placed (pocket ~149), #66 off (pocket ~72) DCO0 - Standard Cell DCO+TDC wafer5 S-3_-2/C0R3 Good 66 35 dies wafer4 DCO0 #136 placed (pocket ~145), #67 off (pocket ~76) DCO0 - Standard Cell DCO+TDC wafer4 S2_1/C0R3 Good 67 DCO0 #135 placed (pocket ~144), #68 off (pocket ~77) DCO0 - Standard Cell DCO+TDC wafer4 S2_0/C0R3 Good 68 DCO0 #134 placed (pocket ~143), #69 off (pocket ~78) DCO0 - Standard Cell DCO+TDC wafer4 S2_-1/C0R3 Good 69 DCO0 #133 placed (pocket ~142), #70 off (pocket ~79) DCO0 - Standard Cell DCO+TDC wafer4 S2_-2/C0R3 Good 70 DCO0 #132 placed (pocket ~141), #71 off (pocket ~80) DCO0 - Standard Cell DCO+TDC wafer4 S2_-3/C0R3 Good 71 DCO0 #131 placed (pocket ~140), #72 off (pocket ~81) DCO0 - Standard Cell DCO+TDC wafer4 S1_2/C0R3 Good 72 DCO0 #130 placed (pocket ~139), #73 off (pocket ~82) DCO0 - Standard Cell DCO+TDC wafer4 S1_1/C0R3 Good 73 DCO0 #129 placed (pocket ~138), #74 off (pocket ~83) DCO0 - Standard Cell DCO+TDC wafer4 S1_0/C0R3 Good 74 DCO0 #128 placed (pocket ~137), #75 off (pocket ~84) DCO0 - Standard Cell DCO+TDC wafer4 S1_-1/C0R3 Good 75 DCO0 #127 placed (pocket ~136), #76 off (pocket ~85) DCO0 - Standard Cell DCO+TDC wafer4 S1_-2/C0R3 Good 76 DCO0 #126 placed (pocket ~135), #77 off (pocket ~86) DCO0 - Standard Cell DCO+TDC wafer4 S1_-3/C0R3 Good 77 DCO0 #125 placed (pocket ~134), #78 off (pocket ~87) DCO0 - Standard Cell DCO+TDC wafer4 S1_-4/C0R3 Good 78 DCO0 #124 placed (pocket ~133), #79 off (pocket ~88) DCO0 - Standard Cell DCO+TDC wafer4 S0_2/C0R3 Good 79 DCO0 #123 placed (pocket ~132), #80 off (pocket ~89) DCO0 - Standard Cell DCO+TDC wafer4 S0_1/C0R3 Good 80 DCO0 #122 placed (pocket ~131), #81 off (pocket ~90) DCO0 - Standard Cell DCO+TDC wafer4 S0_0/C0R3 Placed, unverified 81 DCO0 #121 placed (pocket ~130), #82 off (pocket ~91) DCO0 - Standard Cell DCO+TDC wafer4 S0_-1/C0R3 Good 82 DCO0 #120 placed (pocket ~129), #83 off (pocket ~92) DCO0 - Standard Cell DCO+TDC wafer4 S0_-2/C0R3 Good 83 DCO0 #119 placed (pocket ~128), #84 off (pocket ~93) DCO0 - Standard Cell DCO+TDC wafer4 S0_-3/C0R3 Good 84 DCO0 #118 placed (pocket ~127), #85 off (pocket ~94) DCO0 - Standard Cell DCO+TDC wafer4 S0_-4/C0R3 Good 85 DCO0 #117 placed (pocket ~126), #86 off (pocket ~95) DCO0 - Standard Cell DCO+TDC wafer4 S-1_2/C0R3 Good 86 DCO0 #116 placed (pocket ~125), #87 off (pocket ~96) DCO0 - Standard Cell DCO+TDC wafer4 S-1_1/C0R3 Good 87 DCO0 #115 placed (pocket ~124), #88 off (pocket ~97) DCO0 - Standard Cell DCO+TDC wafer4 S-1_0/C0R3 Good 88 DCO0 #114 placed (pocket ~123), #89 off (pocket ~98) DCO0 - Standard Cell DCO+TDC wafer4 S-1_-1/C0R3 Good 89 DCO0 #113 placed (pocket ~122), #90 off (pocket ~99) DCO0 - Standard Cell DCO+TDC wafer4 S-1_-2/C0R3 Good 90 DCO0 #112 placed (pocket ~121), #91 off (pocket ~100) DCO0 - Standard Cell DCO+TDC wafer4 S-1_-3/C0R3 Placed, unverified 91 DCO0 #111 placed (pocket ~120), #92 off (pocket ~101) DCO0 - Standard Cell DCO+TDC wafer4 S-1_-4/C0R3 Good 92 DCO0 #110 placed (pocket ~119), #93 off (pocket ~102) DCO0 - Standard Cell DCO+TDC wafer4 S-2_1/C0R3 Good 93 DCO0 #109 placed (pocket ~118), #94 off (pocket ~103) DCO0 - Standard Cell DCO+TDC wafer4 S-2_0/C0R3 Good 94 DCO0 #108 placed (pocket ~117), #95 off (pocket ~104) DCO0 - Standard Cell DCO+TDC wafer4 S-2_-1/C0R3 Good 95 DCO0 #107 placed (pocket ~116), #96 off (pocket ~105) DCO0 - Standard Cell DCO+TDC wafer4 S-2_-2/C0R3 Good 96 DCO0 #106 placed (pocket ~115), #97 off (pocket ~106) DCO0 - Standard Cell DCO+TDC wafer4 S-2_-3/C0R3 Good 97 DCO0 #105 placed (pocket ~114), #98 off (pocket ~107) DCO0 - Standard Cell DCO+TDC wafer4 S-2_-4/C0R3 Good 98 DCO0 #104 placed (pocket ~113), #99 off (pocket ~108) DCO0 - Standard Cell DCO+TDC wafer4 S-3_0/C0R3 Placed, unverified 99 DCO0 #103 placed (pocket ~112), #100 off (pocket ~109) DCO0 - Standard Cell DCO+TDC wafer4 S-3_-1/C0R3 Good 100 DCO0 #102 placed (pocket ~111), #101 off (pocket ~110) DCO0 - Standard Cell DCO+TDC wafer4 S-3_-2/C0R3 Good 101 35 dies wafer3 DCO0 #101 placed (pocket ~107), #102 off (pocket ~114) DCO0 - Standard Cell DCO+TDC wafer3 S2_1/C0R3 Good 102 DCO0 #100 placed (pocket ~106), #103 off (pocket ~115) DCO0 - Standard Cell DCO+TDC wafer3 S2_0/C0R3 Good 103 DCO0 #99 placed (pocket ~105), #104 off (pocket ~116) DCO0 - Standard Cell DCO+TDC wafer3 S2_-1/C0R3 Good 104 DCO0 #98 placed (pocket ~104), #105 off (pocket ~117) DCO0 - Standard Cell DCO+TDC wafer3 S2_-2/C0R3 Good 105 DCO0 #97 placed (pocket ~103), #106 off (pocket ~118) DCO0 - Standard Cell DCO+TDC wafer3 S2_-3/C0R3 Good 106 DCO0 #96 placed (pocket ~102), #107 off (pocket ~119) DCO0 - Standard Cell DCO+TDC wafer3 S1_2/C0R3 Good 107 DCO0 #95 placed (pocket ~101), #108 off (pocket ~120) DCO0 - Standard Cell DCO+TDC wafer3 S1_1/C0R3 Good 108 DCO0 #94 placed (pocket ~100), #109 off (pocket ~121) DCO0 - Standard Cell DCO+TDC wafer3 S1_0/C0R3 Good 109 DCO0 #93 placed (pocket ~99), #110 off (pocket ~122) DCO0 - Standard Cell DCO+TDC wafer3 S1_-1/C0R3 Good 110 DCO0 #92 placed (pocket ~98), #111 off (pocket ~123) DCO0 - Standard Cell DCO+TDC wafer3 S1_-2/C0R3 Good 111 DCO0 #91 placed (pocket ~97), #112 off (pocket ~124) DCO0 - Standard Cell DCO+TDC wafer3 S1_-3/C0R3 Good 112 DCO0 #90 placed (pocket ~96), #113 off (pocket ~125) DCO0 - Standard Cell DCO+TDC wafer3 S1_-4/C0R3 Good 113 DCO0 #89 placed (pocket ~95), #114 off (pocket ~126) DCO0 - Standard Cell DCO+TDC wafer3 S0_2/C0R3 Good 114 DCO0 #88 placed (pocket ~94), #115 off (pocket ~127) DCO0 - Standard Cell DCO+TDC wafer3 S0_1/C0R3 Good 115 DCO0 #87 placed (pocket ~93), #116 off (pocket ~128) DCO0 - Standard Cell DCO+TDC wafer3 S0_0/C0R3 Good 116 DCO0 #86 placed (pocket ~92), #117 off (pocket ~129) DCO0 - Standard Cell DCO+TDC wafer3 S0_-1/C0R3 Good 117 DCO0 #85 placed (pocket ~91), #118 off (pocket ~130) DCO0 - Standard Cell DCO+TDC wafer3 S0_-2/C0R3 Good 118 DCO0 #84 placed (pocket ~90), #119 off (pocket ~131) DCO0 - Standard Cell DCO+TDC wafer3 S0_-3/C0R3 Good 119 DCO0 #83 placed (pocket ~89), #120 off (pocket ~132) DCO0 - Standard Cell DCO+TDC wafer3 S0_-4/C0R3 Good 120 DCO0 #82 placed (pocket ~88), #121 off (pocket ~133) DCO0 - Standard Cell DCO+TDC wafer3 S-1_2/C0R3 Good 121 DCO0 #81 placed (pocket ~87), #122 off (pocket ~134) DCO0 - Standard Cell DCO+TDC wafer3 S-1_1/C0R3 Good 122 DCO0 #80 placed (pocket ~86), #123 off (pocket ~135) DCO0 - Standard Cell DCO+TDC wafer3 S-1_0/C0R3 Good 123 DCO0 #79 placed (pocket ~85), #124 off (pocket ~136) DCO0 - Standard Cell DCO+TDC wafer3 S-1_-1/C0R3 Good 124 DCO0 #78 placed (pocket ~84), #125 off (pocket ~137) DCO0 - Standard Cell DCO+TDC wafer3 S-1_-2/C0R3 Good 125 DCO0 #77 placed (pocket ~83), #126 off (pocket ~138) DCO0 - Standard Cell DCO+TDC wafer3 S-1_-3/C0R3 Good 126 DCO0 #76 placed (pocket ~82), #127 off (pocket ~139) DCO0 - Standard Cell DCO+TDC wafer3 S-1_-4/C0R3 Good 127 DCO0 #75 placed (pocket ~81), #128 off (pocket ~140) DCO0 - Standard Cell DCO+TDC wafer3 S-2_1/C0R3 Good 128 DCO0 #74 placed (pocket ~80), #129 off (pocket ~141) DCO0 - Standard Cell DCO+TDC wafer3 S-2_0/C0R3 Good 129 DCO0 #73 placed (pocket ~79), #130 off (pocket ~142) DCO0 - Standard Cell DCO+TDC wafer3 S-2_-1/C0R3 Good 130 DCO0 #72 placed (pocket ~78), #131 off (pocket ~143) DCO0 - Standard Cell DCO+TDC wafer3 S-2_-2/C0R3 Good 131 DCO0 #71 placed (pocket ~77), #132 off (pocket ~144) DCO0 - Standard Cell DCO+TDC wafer3 S-2_-3/C0R3 Good 132 DCO0 #70 placed (pocket ~76), #133 off (pocket ~145) DCO0 - Standard Cell DCO+TDC wafer3 S-2_-4/C0R3 Good 133 DCO0 #69 placed (pocket ~75), #134 off (pocket ~146) DCO0 - Standard Cell DCO+TDC wafer3 S-3_0/C0R3 Good 134 DCO0 #68 placed (pocket ~74), #135 off (pocket ~147) DCO0 - Standard Cell DCO+TDC wafer3 S-3_-1/C0R3 Good 135 DCO0 #67 placed (pocket ~73), #136 off (pocket ~148) DCO0 - Standard Cell DCO+TDC wafer3 S-3_-2/C0R3 Good 136 35 dies wafer2 DCO0 #66 placed (pocket ~69), #137 off (pocket ~152) DCO0 - Standard Cell DCO+TDC wafer2 S2_1/C0R3 Good 137 DCO0 #65 placed (pocket ~68), #138 off (pocket ~153) DCO0 - Standard Cell DCO+TDC wafer2 S2_0/C0R3 Good 138 DCO0 #64 placed (pocket ~67), #139 off (pocket ~154) DCO0 - Standard Cell DCO+TDC wafer2 S2_-1/C0R3 Good 139 DCO0 #63 placed (pocket ~66), #140 off (pocket ~155) DCO0 - Standard Cell DCO+TDC wafer2 S2_-2/C0R3 Good 140 DCO0 #62 placed (pocket ~65), #141 off (pocket ~156) DCO0 - Standard Cell DCO+TDC wafer2 S2_-3/C0R3 Placed, unverified 141 DCO0 #61 placed (pocket ~64), #142 off (pocket ~157) DCO0 - Standard Cell DCO+TDC wafer2 S1_2/C0R3 Good 142 DCO0 #60 placed (pocket ~63), #143 off (pocket ~158) DCO0 - Standard Cell DCO+TDC wafer2 S1_1/C0R3 Good 143 DCO0 #59 placed (pocket ~62), #144 off (pocket ~159) DCO0 - Standard Cell DCO+TDC wafer2 S1_0/C0R3 Good 144 DCO0 #58 placed (pocket ~61), #145 off (pocket ~160) DCO0 - Standard Cell DCO+TDC wafer2 S1_-1/C0R3 Good 145 DCO0 #57 placed (pocket ~60), #146 off (pocket ~161) DCO0 - Standard Cell DCO+TDC wafer2 S1_-2/C0R3 Good 146 DCO0 #56 placed (pocket ~59), #147 off (pocket ~162) DCO0 - Standard Cell DCO+TDC wafer2 S1_-3/C0R3 Good 147 DCO0 #55 placed (pocket ~58), #148 off (pocket ~163) DCO0 - Standard Cell DCO+TDC wafer2 S1_-4/C0R3 Good 148 DCO0 #54 placed (pocket ~57), #149 off (pocket ~164) DCO0 - Standard Cell DCO+TDC wafer2 S0_2/C0R3 Good 149 DCO0 #53 placed (pocket ~56), #150 off (pocket ~165) DCO0 - Standard Cell DCO+TDC wafer2 S0_1/C0R3 Good 150 DCO0 #52 placed (pocket ~55), #151 off (pocket ~166) DCO0 - Standard Cell DCO+TDC wafer2 S0_0/C0R3 Good 151 DCO0 #51 placed (pocket ~54), #152 off (pocket ~167) DCO0 - Standard Cell DCO+TDC wafer2 S0_-1/C0R3 Good 152 DCO0 #50 placed (pocket ~53), #153 off (pocket ~168) DCO0 - Standard Cell DCO+TDC wafer2 S0_-2/C0R3 Placed, unverified 153 DCO0 #49 placed (pocket ~52), #154 off (pocket ~169) DCO0 - Standard Cell DCO+TDC wafer2 S0_-3/C0R3 Good 154 DCO0 #48 placed (pocket ~51), #155 off (pocket ~170) DCO0 - Standard Cell DCO+TDC wafer2 S0_-4/C0R3 Good 155 DCO0 #47 placed (pocket ~50), #156 off (pocket ~171) DCO0 - Standard Cell DCO+TDC wafer2 S-1_2/C0R3 Good 156 DCO0 #46 placed (pocket ~49), #157 off (pocket ~172) DCO0 - Standard Cell DCO+TDC wafer2 S-1_1/C0R3 Good 157 DCO0 #45 placed (pocket ~48), #158 off (pocket ~173) DCO0 - Standard Cell DCO+TDC wafer2 S-1_0/C0R3 Good 158 DCO0 #44 placed (pocket ~47), #159 off (pocket ~174) DCO0 - Standard Cell DCO+TDC wafer2 S-1_-1/C0R3 Good 159 DCO0 #43 placed (pocket ~46), #160 off (pocket ~175) DCO0 - Standard Cell DCO+TDC wafer2 S-1_-2/C0R3 Good 160 DCO0 #42 placed (pocket ~45), #161 off (pocket ~176) DCO0 - Standard Cell DCO+TDC wafer2 S-1_-3/C0R3 Good 161 DCO0 #41 placed (pocket ~44), #162 off (pocket ~177) DCO0 - Standard Cell DCO+TDC wafer2 S-1_-4/C0R3 Good 162 DCO0 #40 placed (pocket ~43), #163 off (pocket ~178) DCO0 - Standard Cell DCO+TDC wafer2 S-2_1/C0R3 Good 163 DCO0 #39 placed (pocket ~42), #164 off (pocket ~179) DCO0 - Standard Cell DCO+TDC wafer2 S-2_0/C0R3 Good 164 DCO0 #38 placed (pocket ~41), #165 off (pocket ~180) DCO0 - Standard Cell DCO+TDC wafer2 S-2_-2/C0R3 Good 165 DCO0 #37 placed (pocket ~40), #166 off (pocket ~181) DCO0 - Standard Cell DCO+TDC wafer2 S-2_-3/C0R3 Good 166 DCO0 #36 placed (pocket ~39), #167 off (pocket ~182) DCO0 - Standard Cell DCO+TDC wafer2 S-2_-4/C0R3 Good 167 DCO0 #35 placed (pocket ~38), #168 off (pocket ~183) DCO0 - Standard Cell DCO+TDC wafer2 S-3_0/C0R3 Good 168 DCO0 #34 placed (pocket ~37), #169 off (pocket ~184) DCO0 - Standard Cell DCO+TDC wafer2 S-3_-1/C0R3 Good 169 DCO0 #33 placed (pocket ~36), #170 off (pocket ~185) DCO0 - Standard Cell DCO+TDC wafer2 S-3_-2/C0R3 Good 170 34 dies wafer1 DCO0 #32 placed (pocket ~32), #171 off (pocket ~189) DCO0 - Standard Cell DCO+TDC wafer1 S2_1/C0R3 Good 171 DCO0 #31 placed (pocket ~31), #172 off (pocket ~190) DCO0 - Standard Cell DCO+TDC wafer1 S2_0/C0R3 Good 172 DCO0 #30 placed (pocket ~30), #173 off (pocket ~191) DCO0 - Standard Cell DCO+TDC wafer1 S2_-1/C0R3 Good 173 DCO0 #29 placed (pocket ~29), #174 off (pocket ~192) DCO0 - Standard Cell DCO+TDC wafer1 S2_-2/C0R3 Good 174 DCO0 #28 placed (pocket ~28), #175 off (pocket ~193) DCO0 - Standard Cell DCO+TDC wafer1 S2_-3/C0R3 Good 175 DCO0 #27 placed (pocket ~27), #176 off (pocket ~194) DCO0 - Standard Cell DCO+TDC wafer1 S1_2/C0R3 Good 176 DCO0 #26 placed (pocket ~26), #177 off (pocket ~195) DCO0 - Standard Cell DCO+TDC wafer1 S1_1/C0R3 Good 177 DCO0 #25 placed (pocket ~25), #178 off (pocket ~196) DCO0 - Standard Cell DCO+TDC wafer1 S1_0/C0R3 Good 178 DCO0 #24 placed (pocket ~24), #179 off (pocket ~197) DCO0 - Standard Cell DCO+TDC wafer1 S1_-1/C0R3 Good 179 DCO0 #23 placed (pocket ~23), #180 off (pocket ~198) DCO0 - Standard Cell DCO+TDC wafer1 S1_-2/C0R3 Good 180 DCO0 #22 placed (pocket ~22), #181 off (pocket ~199) DCO0 - Standard Cell DCO+TDC wafer1 S1_-3/C0R3 Good 181 DCO0 #21 placed (pocket ~21), #182 off (pocket ~200) DCO0 - Standard Cell DCO+TDC wafer1 S1_-4/C0R3 Good 182 DCO0 #20 placed (pocket ~20), #183 off (pocket ~201) DCO0 - Standard Cell DCO+TDC wafer1 S0_2/C0R3 Good 183 DCO0 #19 placed (pocket ~19), #184 off (pocket ~202) DCO0 - Standard Cell DCO+TDC wafer1 S0_1/C0R3 Good 184 DCO0 #18 placed (pocket ~18), #185 off (pocket ~203) DCO0 - Standard Cell DCO+TDC wafer1 S0_0/C0R3 Good 185 DCO0 #17 placed (pocket ~17), #186 off (pocket ~204) DCO0 - Standard Cell DCO+TDC wafer1 S0_-1/C0R3 Good 186 DCO0 #16 placed (pocket ~16), #187 off (pocket ~205) DCO0 - Standard Cell DCO+TDC wafer1 S0_-2/C0R3 Good 187 DCO0 #15 placed (pocket ~15), #188 off (pocket ~206) DCO0 - Standard Cell DCO+TDC wafer1 S0_-3/C0R3 Good 188 DCO0 #14 placed (pocket ~14), #189 off (pocket ~207) DCO0 - Standard Cell DCO+TDC wafer1 S0_-4/C0R3 Good 189 DCO0 #13 placed (pocket ~13), #190 off (pocket ~208) DCO0 - Standard Cell DCO+TDC wafer1 S-1_2/C0R3 Good 190 DCO0 #12 placed (pocket ~12), #191 off (pocket ~209) DCO0 - Standard Cell DCO+TDC wafer1 S-1_1/C0R3 Good 191 DCO0 #11 placed (pocket ~11), #192 off (pocket ~210) DCO0 - Standard Cell DCO+TDC wafer1 S-1_0/C0R3 Good 192 DCO0 #10 placed (pocket ~10), #193 off (pocket ~211) DCO0 - Standard Cell DCO+TDC wafer1 S-1_-1/C0R3 Good 193 DCO0 #9 placed (pocket ~9), #194 off (pocket ~212) DCO0 - Standard Cell DCO+TDC wafer1 S-1_-2/C0R3 Good 194 DCO0 #8 placed (pocket ~8), #195 off (pocket ~213) DCO0 - Standard Cell DCO+TDC wafer1 S-1_-3/C0R3 Good 195 DCO0 #7 placed (pocket ~7), #196 off (pocket ~214) DCO0 - Standard Cell DCO+TDC wafer1 S-1_-4/C0R3 Good 196 DCO0 #6 placed (pocket ~6), #197 off (pocket ~215) DCO0 - Standard Cell DCO+TDC wafer1 S-2_1/C0R3 Good 197 DCO0 #5 placed (pocket ~5), #198 off (pocket ~216) DCO0 - Standard Cell DCO+TDC wafer1 S-2_0/C0R3 Good 198 DCO0 #4 placed (pocket ~4), #199 off (pocket ~217) DCO0 - Standard Cell DCO+TDC wafer1 S-2_-1/C0R3 Good 199 DCO0 #3 placed (pocket ~3), #200 off (pocket ~218) DCO0 - Standard Cell DCO+TDC wafer1 S-2_-4/C0R3 Good 200 DCO0 #2 placed (pocket ~2), #201 off (pocket ~219) DCO0 - Standard Cell DCO+TDC wafer1 S-3_0/C0R3 Good 201 31 dies

Every pocket

PocketDieWaferReticleNote
1empty
2empty
3empty
41wafer6S2_1/C0R3
52wafer6S2_0/C0R3
63wafer6S2_-1/C0R3
74wafer6S2_-2/C0R3
85wafer6S2_-3/C0R3
96wafer6S1_2/C0R3
107wafer6S1_1/C0R3
118wafer6S1_0/C0R3
129wafer6S1_-1/C0R3
1310wafer6S1_-2/C0R3
1411wafer6S1_-3/C0R3
1512wafer6S1_-4/C0R3
1613wafer6S0_2/C0R3
1714wafer6S0_1/C0R3
1815wafer6S0_0/C0R3
1916wafer6S0_-1/C0R3
2017wafer6S0_-2/C0R3
2118wafer6S0_-3/C0R3
2219wafer6S0_-4/C0R3
2320wafer6S-1_2/C0R3
2421wafer6S-1_1/C0R3
2522wafer6S-1_0/C0R3
2623wafer6S-1_-1/C0R3
2724wafer6S-1_-2/C0R3
2825wafer6S-1_-3/C0R3
2926wafer6S-1_-4/C0R3
3027wafer6S-2_1/C0R3
3128wafer6S-2_0/C0R3
3229wafer6S-2_-1/C0R3? Unverified
3330wafer6S-2_-2/C0R3
3431wafer6S-3_0/C0R3
35empty
36empty
37empty
3832wafer5S2_1/C0R3
3933wafer5S2_0/C0R3
4034wafer5S2_-1/C0R3
4135wafer5S2_-2/C0R3
4236wafer5S2_-3/C0R3
4337wafer5S1_2/C0R3
4438wafer5S1_1/C0R3
4539wafer5S1_0/C0R3
4640wafer5S1_-1/C0R3
4741wafer5S1_-2/C0R3
4842wafer5S1_-3/C0R3
4943wafer5S1_-4/C0R3
5044wafer5S0_2/C0R3
5145wafer5S0_1/C0R3
5246wafer5S0_0/C0R3
5347wafer5S0_-1/C0R3
5448wafer5S0_-2/C0R3
5549wafer5S0_-3/C0R3
5650wafer5S0_-4/C0R3
5751wafer5S-1_2/C0R3
5852wafer5S-1_1/C0R3
5953wafer5S-1_0/C0R3
6054wafer5S-1_-1/C0R3
6155wafer5S-1_-2/C0R3
6256wafer5S-1_-3/C0R3
6357wafer5S-1_-4/C0R3
6458wafer5S-2_1/C0R3
6559wafer5S-2_0/C0R3
6660wafer5S-2_-1/C0R3
6761wafer5S-2_-2/C0R3
6862wafer5S-2_-3/C0R3
6963wafer5S-2_-4/C0R3
7064wafer5S-3_0/C0R3
7165wafer5S-3_-1/C0R3
7266wafer5S-3_-2/C0R3
73empty
74empty
75empty
7667wafer4S2_1/C0R3
7768wafer4S2_0/C0R3
7869wafer4S2_-1/C0R3
7970wafer4S2_-2/C0R3
8071wafer4S2_-3/C0R3
8172wafer4S1_2/C0R3
8273wafer4S1_1/C0R3
8374wafer4S1_0/C0R3
8475wafer4S1_-1/C0R3
8576wafer4S1_-2/C0R3
8677wafer4S1_-3/C0R3
8778wafer4S1_-4/C0R3
8879wafer4S0_2/C0R3
8980wafer4S0_1/C0R3
9081wafer4S0_0/C0R3? Unverified
9182wafer4S0_-1/C0R3
9283wafer4S0_-2/C0R3
9384wafer4S0_-3/C0R3
9485wafer4S0_-4/C0R3
9586wafer4S-1_2/C0R3
9687wafer4S-1_1/C0R3
9788wafer4S-1_0/C0R3
9889wafer4S-1_-1/C0R3
9990wafer4S-1_-2/C0R3
10091wafer4S-1_-3/C0R3? Unverified
10192wafer4S-1_-4/C0R3
10293wafer4S-2_1/C0R3
10394wafer4S-2_0/C0R3
10495wafer4S-2_-1/C0R3
10596wafer4S-2_-2/C0R3
10697wafer4S-2_-3/C0R3
10798wafer4S-2_-4/C0R3
10899wafer4S-3_0/C0R3? Unverified
109100wafer4S-3_-1/C0R3
110101wafer4S-3_-2/C0R3
111empty
112empty
113empty
114102wafer3S2_1/C0R3
115103wafer3S2_0/C0R3
116104wafer3S2_-1/C0R3
117105wafer3S2_-2/C0R3
118106wafer3S2_-3/C0R3
119107wafer3S1_2/C0R3
120108wafer3S1_1/C0R3
121109wafer3S1_0/C0R3
122110wafer3S1_-1/C0R3
123111wafer3S1_-2/C0R3
124112wafer3S1_-3/C0R3
125113wafer3S1_-4/C0R3
126114wafer3S0_2/C0R3
127115wafer3S0_1/C0R3
128116wafer3S0_0/C0R3
129117wafer3S0_-1/C0R3
130118wafer3S0_-2/C0R3
131119wafer3S0_-3/C0R3
132120wafer3S0_-4/C0R3
133121wafer3S-1_2/C0R3
134122wafer3S-1_1/C0R3
135123wafer3S-1_0/C0R3
136124wafer3S-1_-1/C0R3
137125wafer3S-1_-2/C0R3
138126wafer3S-1_-3/C0R3
139127wafer3S-1_-4/C0R3
140128wafer3S-2_1/C0R3
141129wafer3S-2_0/C0R3
142130wafer3S-2_-1/C0R3
143131wafer3S-2_-2/C0R3
144132wafer3S-2_-3/C0R3
145133wafer3S-2_-4/C0R3
146134wafer3S-3_0/C0R3
147135wafer3S-3_-1/C0R3
148136wafer3S-3_-2/C0R3
149empty
150empty
151empty
152137wafer2S2_1/C0R3
153138wafer2S2_0/C0R3
154139wafer2S2_-1/C0R3
155140wafer2S2_-2/C0R3
156141wafer2S2_-3/C0R3? Unverified
157142wafer2S1_2/C0R3
158143wafer2S1_1/C0R3
159144wafer2S1_0/C0R3
160145wafer2S1_-1/C0R3
161146wafer2S1_-2/C0R3
162147wafer2S1_-3/C0R3
163148wafer2S1_-4/C0R3
164149wafer2S0_2/C0R3
165150wafer2S0_1/C0R3
166151wafer2S0_0/C0R3
167152wafer2S0_-1/C0R3
168153wafer2S0_-2/C0R3? Unverified
169154wafer2S0_-3/C0R3
170155wafer2S0_-4/C0R3
171156wafer2S-1_2/C0R3
172157wafer2S-1_1/C0R3
173158wafer2S-1_0/C0R3
174159wafer2S-1_-1/C0R3
175160wafer2S-1_-2/C0R3
176161wafer2S-1_-3/C0R3
177162wafer2S-1_-4/C0R3
178163wafer2S-2_1/C0R3
179164wafer2S-2_0/C0R3
180165wafer2S-2_-2/C0R3
181166wafer2S-2_-3/C0R3
182167wafer2S-2_-4/C0R3
183168wafer2S-3_0/C0R3
184169wafer2S-3_-1/C0R3
185170wafer2S-3_-2/C0R3
186empty
187empty
188empty
189171wafer1S2_1/C0R3
190172wafer1S2_0/C0R3
191173wafer1S2_-1/C0R3
192174wafer1S2_-2/C0R3
193175wafer1S2_-3/C0R3
194176wafer1S1_2/C0R3
195177wafer1S1_1/C0R3
196178wafer1S1_0/C0R3
197179wafer1S1_-1/C0R3
198180wafer1S1_-2/C0R3
199181wafer1S1_-3/C0R3
200182wafer1S1_-4/C0R3
201183wafer1S0_2/C0R3
202184wafer1S0_1/C0R3
203185wafer1S0_0/C0R3
204186wafer1S0_-1/C0R3
205187wafer1S0_-2/C0R3
206188wafer1S0_-3/C0R3
207189wafer1S0_-4/C0R3
208190wafer1S-1_2/C0R3
209191wafer1S-1_1/C0R3
210192wafer1S-1_0/C0R3
211193wafer1S-1_-1/C0R3
212194wafer1S-1_-2/C0R3
213195wafer1S-1_-3/C0R3
214196wafer1S-1_-4/C0R3
215197wafer1S-2_1/C0R3
216198wafer1S-2_0/C0R3
217199wafer1S-2_-1/C0R3
218200wafer1S-2_-4/C0R3
219201wafer1S-3_0/C0R3
220202wafer6S-3_-2/C0R3